From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Sat, 4 Dec 2021 17:46:23 +0000 (+0000)
Subject: test in SimState for access to RADIX memory, bypass and get contents direct
X-Git-Tag: sv_maxu_works-initial~668
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=d8943f8852b65101ca6e495a386d68b6dec98be6;p=openpower-isa.git

test in SimState for access to RADIX memory, bypass and get contents direct
---

diff --git a/src/openpower/test/state.py b/src/openpower/test/state.py
index 77e881c2..ee884f81 100644
--- a/src/openpower/test/state.py
+++ b/src/openpower/test/state.py
@@ -23,6 +23,7 @@ methods, the use of yield from/yield is required.
 
 
 from openpower.decoder.power_enums import XER_bits
+from openpower.decoder.isa.radixmmu import RADIX
 from openpower.util import log
 import os
 import sys
@@ -216,12 +217,15 @@ class SimState(State):
     def get_mem(self):
         if False:
             yield
-        keys = list(self.sim.mem.mem.keys())
+        mem = self.sim.mem
+        if isinstance(mem, RADIX):
+            mem = mem.mem
+        keys = list(mem.mem.keys())
         self.mem = {}
         # from each address in the underlying mem-simulated dictionary
         # issue a 64-bit LD (with no byte-swapping)
         for k in keys:
-            data = self.sim.mem.ld(k*8, 8, False)
+            data = mem.ld(k*8, 8, False)
             self.mem[k*8] = data