From: Gabe Black <gblack@eecs.umich.edu>
Date: Mon, 12 Nov 2007 22:38:02 +0000 (-0800)
Subject: X86: Make some of the bits of CR0 do what they're supposed to.
X-Git-Tag: m5_2.0_beta5~84^2~17
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=d89d80a5d0bea8a17149abc490ba0d46bff5b11a;p=gem5.git

X86: Make some of the bits of CR0 do what they're supposed to.

--HG--
extra : convert_revision : 13e79ef1ef09bd842d5e075e31f98ab2a4357901
---

diff --git a/src/arch/x86/miscregfile.cc b/src/arch/x86/miscregfile.cc
index e2c39c7cd..cd76e96aa 100644
--- a/src/arch/x86/miscregfile.cc
+++ b/src/arch/x86/miscregfile.cc
@@ -154,7 +154,30 @@ void MiscRegFile::setRegNoEffect(int miscReg, const MiscReg &val)
 void MiscRegFile::setReg(int miscReg,
         const MiscReg &val, ThreadContext * tc)
 {
-    setRegNoEffect(miscReg, val);
+    MiscReg newVal = val;
+    switch(miscReg)
+    {
+      case MISCREG_CR0:
+        CR0 toggled = regVal[miscReg] ^ val;
+        CR0 newCR0 = val;
+        Efer efer = regVal[MISCREG_EFER];
+        if (toggled.pg && efer.lme) {
+            if (newCR0.pg) {
+                //Turning on long mode
+                efer.lma = 1;
+                regVal[MISCREG_EFER] = efer;
+            } else {
+                //Turning off long mode
+                efer.lma = 0;
+                regVal[MISCREG_EFER] = efer;
+            }
+        }
+        //This must always be 1.
+        newCR0.et = 1;
+        newVal = newCR0;
+        break;
+    }
+    setRegNoEffect(miscReg, newVal);
 }
 
 void MiscRegFile::serialize(std::ostream & os)