From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Thu, 25 Jun 2020 19:25:13 +0000 (+0100)
Subject: add beginnings of Pi2LSUI
X-Git-Tag: div_pipeline~275
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=d8c345b5086662cba2518e608c550718efdabf66;p=soc.git

add beginnings of Pi2LSUI
---

diff --git a/src/soc/experiment/pi2ls.py b/src/soc/experiment/pi2ls.py
index 7b2e6d07..ac2936bb 100644
--- a/src/soc/experiment/pi2ls.py
+++ b/src/soc/experiment/pi2ls.py
@@ -19,3 +19,17 @@
     st.data/64                   x_st_data_i
     st.ok/1                      probably kinda redundant, set to x_st_i
 """
+
+from soc.minerva.units.loadstore import LoadStoreUnitInterface
+from soc.experiment.pimem import PortInterface
+from nmigen import Elaboratable, Module, Signal
+
+class Pi2LSUI(Elaboratable):
+
+    def __init__(self, name, regwid=64, addrwid=48):
+        self.pi = PortInterface(name="%s_pi", regwid, addrwid)
+        self.lsui = LoadStoreUnitInterface(addrwid, 4, regwid)
+
+    def elaborate(self, platform):
+        m = Module()
+        return m