From: Ali Saidi <saidi@eecs.umich.edu>
Date: Fri, 1 Jun 2007 17:44:24 +0000 (-0400)
Subject: don't generate trace data unless tracing is on
X-Git-Tag: m5_2.0_beta4~384^2^2~1
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=d8c487c40112590b541dc1e74b435ecb8fe8cef8;p=gem5.git

don't generate trace data unless tracing is on

--HG--
extra : convert_revision : 3953ace8d481d758d6e0d89183c0a7e7bebcf681
---

diff --git a/src/cpu/o3/fetch_impl.hh b/src/cpu/o3/fetch_impl.hh
index e16f97558..895b4a46c 100644
--- a/src/cpu/o3/fetch_impl.hh
+++ b/src/cpu/o3/fetch_impl.hh
@@ -1151,10 +1151,14 @@ DefaultFetch<Impl>::fetch(bool &status_change)
             DPRINTF(Fetch, "[tid:%i]: Instruction is: %s\n",
                     tid, instruction->staticInst->disassemble(fetch_PC));
 
+#if TRACING_ON
             instruction->traceData =
                 Trace::getInstRecord(curTick, cpu->tcBase(tid),
                                      instruction->staticInst,
                                      instruction->readPC());
+#elif
+            instruction->traceData = NULL;
+#endif
 
             ///FIXME This needs to be more robust in dealing with delay slots
 #if !ISA_HAS_DELAY_SLOT