From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Sat, 20 Mar 2021 18:58:54 +0000 (+0000)
Subject: more pseudocode in TestIssuer
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=d8c5d4927fc23a8d04da0528c39db30af6d86d9b;p=soc.git

more pseudocode in TestIssuer
---

diff --git a/src/soc/simple/issuer.py b/src/soc/simple/issuer.py
index 3d6c3ce6..a58a44a0 100644
--- a/src/soc/simple/issuer.py
+++ b/src/soc/simple/issuer.py
@@ -343,9 +343,15 @@ class TestIssuerInternal(Elaboratable):
                     # detected, in order to trigger - and wait for - the
                     # predicate reading.
                     pmode = pdecode2.rm_dec.predmode
-                    sv_ptype = pdecode2.dec.op.SV_Ptype
-                    srcpred = pdecode2.rm_dec.srcpred
-                    dstpred = pdecode2.rm_dec.dstpred
+                    """
+                    if pmode != SVP64PredMode.ALWAYS.value:
+                        fire predicate loading FSM and wait before
+                        moving to INSN_READY
+                    else:
+                        sync += self.srcmask.eq(-1) # set to all 1s
+                        sync += self.dstmask.eq(-1) # set to all 1s
+                        m.next = "INSN_READY"
+                    """
 
             with m.State("INSN_READY"):
                 # hand over the instruction, to be decoded