From: lkcl <lkcl@web>
Date: Sun, 24 Jan 2021 13:42:04 +0000 (+0000)
Subject: (no commit message)
X-Git-Tag: convert-csv-opcode-to-binary~353
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=d8ccaba0e2b8679c76b690130cb210f0053ea725;p=libreriscv.git

---

diff --git a/openpower/sv/ldst.mdwn b/openpower/sv/ldst.mdwn
index 7317a37ea..14fc02e16 100644
--- a/openpower/sv/ldst.mdwn
+++ b/openpower/sv/ldst.mdwn
@@ -308,15 +308,17 @@ permutations of vector selection, to identify above asm-syntax:
 
      imm(RA)  RT.v   RA.v   nonstrided
          sv.ld r#.v, ofst(r#2.v) -> r#2 is a vector of addresses
+           mem@     0+r#2   offs+(r#2+1)  offs+(r#2+2)
+           destreg  r#      r#+1          r#+2
      imm(RA)  RT.s   RA.v   nonstrided
          sv.ld r#, ofst(r#2.v) -> r#2 is a vector of addresses
            (dest r# is scalar) -> VSELECT mode
      imm(RA)  RT.v   RA.s   fixed stride: unit or element
          sv.ld r#.v, ofst(r#2).v -> whole vector is at ofst+r#2
-           mem      0    1    2
+           mem@r#   +0   +1   +2
            destreg  r#   r#+1 r#+2
          sv.ld/els r#.v, ofst(r#2).v -> vector at ofst*elidx+r#2
-           mem      0 ...    offs ...   offs*2
+           mem@r#   +0 ...   +offs ...  +offs*2
            destreg  r#       r#+1       r#+2
      imm(RA)  RT.s   RA.s   not vectorised
          sv.ld r#, ofst(r#2)