From: whitequark <whitequark@whitequark.org>
Date: Wed, 8 Jul 2020 09:08:00 +0000 (+0000)
Subject: vendor.xilinx_{7series,ultrascale}: remove `grade` property.
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=d8cf42d7fe34b5081d97c4e829a3e906b7850fe3;p=nmigen.git

vendor.xilinx_{7series,ultrascale}: remove `grade` property.

This was added in commit bfd4538d based on a misunderstanding of how
Xilinx part numbers work.
 * non-ultrascale 7-series parts don't have temperature grades;
 * ultrascale parts have temperature grade as a part of speed grade.
---

diff --git a/nmigen/vendor/xilinx_7series.py b/nmigen/vendor/xilinx_7series.py
index 0bf5424..6e3017f 100644
--- a/nmigen/vendor/xilinx_7series.py
+++ b/nmigen/vendor/xilinx_7series.py
@@ -51,7 +51,6 @@ class Xilinx7SeriesPlatform(TemplatedPlatform):
     device  = abstractproperty()
     package = abstractproperty()
     speed   = abstractproperty()
-    grade   = None
 
     required_tools = ["vivado"]
     file_templates = {
@@ -73,7 +72,7 @@ class Xilinx7SeriesPlatform(TemplatedPlatform):
         """,
         "{{name}}.tcl": r"""
             # {{autogenerated}}
-            create_project -force -name {{name}} -part {{platform.device}}{{platform.package}}-{{platform.speed}}{{"-" + platform.grade if platform.grade else ""}}
+            create_project -force -name {{name}} -part {{platform.device}}{{platform.package}}-{{platform.speed}}
             {% for file in platform.iter_extra_files(".v", ".sv", ".vhd", ".vhdl") -%}
                 add_files {{file|tcl_escape}}
             {% endfor %}
diff --git a/nmigen/vendor/xilinx_ultrascale.py b/nmigen/vendor/xilinx_ultrascale.py
index 6f90517..19bbeae 100644
--- a/nmigen/vendor/xilinx_ultrascale.py
+++ b/nmigen/vendor/xilinx_ultrascale.py
@@ -51,7 +51,6 @@ class XilinxUltraScalePlatform(TemplatedPlatform):
     device  = abstractproperty()
     package = abstractproperty()
     speed   = abstractproperty()
-    grade   = None
 
     required_tools = ["vivado"]
     file_templates = {
@@ -73,7 +72,7 @@ class XilinxUltraScalePlatform(TemplatedPlatform):
         """,
         "{{name}}.tcl": r"""
             # {{autogenerated}}
-            create_project -force -name {{name}} -part {{platform.device}}-{{platform.package}}-{{platform.speed}}{{"-" + platform.grade if platform.grade else ""}}
+            create_project -force -name {{name}} -part {{platform.device}}-{{platform.package}}-{{platform.speed}}
             {% for file in platform.iter_extra_files(".v", ".sv", ".vhd", ".vhdl") -%}
                 add_files {{file|tcl_escape}}
             {% endfor %}