From: lkcl <lkcl@web>
Date: Thu, 6 Oct 2022 17:41:17 +0000 (+0100)
Subject: (no commit message)
X-Git-Tag: opf_rfc_ls005_v1~145
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=d8d3394bbfba6be0d57c52434986e6987c1791d4;p=libreriscv.git

---

diff --git a/nlnet_2022_ongoing/discussion.mdwn b/nlnet_2022_ongoing/discussion.mdwn
index 7a98ae756..70b1dc300 100644
--- a/nlnet_2022_ongoing/discussion.mdwn
+++ b/nlnet_2022_ongoing/discussion.mdwn
@@ -50,8 +50,13 @@ https://libre-soc.org/nlnet_2021_lip6_vlsi/ 2021-08-049.
 sky130
 is far too small an allocation (12 mm^2 when we need around 100), we
 really need sky90 which as i understand is still being negotiated and set up.
+
 Given the amount of time ls180 took (I have to admit it was a major time-sink for me)
-I am happy to wait until coriolis2 is more feature-ready.  Powerful FPGAs will
+as a "learning exercise" the 2019-10-029 project was perfect.
+However as far as "value for money" is concerned, a repeat is honestly
+less valuable.  That said: when it is ready, RED Semiconductor
+*will* be picking up the Libre-SOC core and taking it to Silicon
+(28 nm or below).  For this Grant Proposal, powerful FPGAs will
 get us a long way.
 
 The concrete outcomes: