From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Wed, 2 Sep 2020 22:08:27 +0000 (+0100)
Subject: when mtocrf FXM is 0, the CR has to be set to CR7
X-Git-Tag: semi_working_ecp5~210
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=d8d9180714586ad9c4e40daa846ded7628092463;p=soc.git

when mtocrf FXM is 0, the CR has to be set to CR7
---

diff --git a/src/soc/decoder/power_decoder2.py b/src/soc/decoder/power_decoder2.py
index 8ef8959a..edbbf878 100644
--- a/src/soc/decoder/power_decoder2.py
+++ b/src/soc/decoder/power_decoder2.py
@@ -586,7 +586,10 @@ class DecodeCROut(Elaboratable):
                     with m.If(move_one):
                         # must one-hot the FXM field
                         comb += ppick.i.eq(self.dec.FXM)
-                        comb += self.whole_reg.data.eq(ppick.o)
+                        with m.If(ppick.en_o):
+                            comb += self.whole_reg.data.eq(ppick.o)
+                        with m.Else():
+                            comb += self.whole_reg.data.eq(0b00000001) # CR7
                     with m.Else():
                         comb += self.whole_reg.data.eq(self.dec.FXM)
                 with m.Else():
diff --git a/src/soc/fu/cr/test/test_pipe_caller.py b/src/soc/fu/cr/test/test_pipe_caller.py
index 8e71a3a8..8b8a4616 100644
--- a/src/soc/fu/cr/test/test_pipe_caller.py
+++ b/src/soc/fu/cr/test/test_pipe_caller.py
@@ -134,6 +134,19 @@ class CRTestCase(TestAccumulatorBase):
         p.assembly = '\n'.join(dis)+'\n'
         self.add_case(p, initial_regs=initial_regs, initial_cr=cr)
 
+    def case_mtocrf_regression_2(self):
+        """microwatt 1.bin regression, zero fxm
+           mtocrf 0,16     14928:   21 09 10 7e     .long 0x7e100921
+        """
+        dis = ["mtocrf 16, 0"]
+        lst = bytes([0x21, 0x09, 0x10, 0x7e]) # 0x7e100921
+        cr = 0x3F089F7F
+        initial_regs = [0] * 32
+        initial_regs[16] = 0x0001C020
+        p = Program(lst, bigendian)
+        p.assembly = '\n'.join(dis)+'\n'
+        self.add_case(p, initial_regs=initial_regs, initial_cr=cr)
+
     def case_mfocrf_1(self):
         lst = [f"mfocrf 2, 1"]
         cr = 0x1234