From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Wed, 23 Jun 2021 11:26:37 +0000 (+0100)
Subject: use SHL64 function for shift because "<<" operator doesnt exist in
X-Git-Tag: xlen-bcd~418
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=d8dce8950c84fc970073e9cf9a7051905d0924a8;p=openpower-isa.git

use SHL64 function for shift because "<<" operator doesnt exist in
v3.0B pseudocode syntax
---

diff --git a/openpower/isa/svfixedload.mdwn b/openpower/isa/svfixedload.mdwn
index 58a55ec9..cdd7eadf 100644
--- a/openpower/isa/svfixedload.mdwn
+++ b/openpower/isa/svfixedload.mdwn
@@ -1,4 +1,6 @@
-<!-- This defines Load instructions described in SVP64 -->
+<!-- This defines SVP64 bit-reversed Load instructions -->
+<!-- They are augmented variants of v3.0B Load instructions -->
+<!-- and are designed specifically for Cooley-Tukey FFT/DCT -->
 
 # Load Byte and Zero
 
@@ -9,7 +11,8 @@ SVD-Form
 Pseudo-code:
 
     b <- (RA|0)
-    EA <- b + (bitrev(srcstep, VL) * EXTS(D)) << RC
+    n <- (RC)[58:63]
+    EA <- b + SHL64(bitrev(srcstep, VL) * EXTS(D), n)
     RT <- [0]*56 || MEM(EA, 1)
 
 Special Registers Altered:
@@ -24,7 +27,8 @@ SVD-Form
 
 Pseudo-code:
 
-    EA <- (RA) + (bitrev(srcstep, VL) * EXTS(D)) << RC
+    n <- (RC)[58:63]
+    EA <- (RA) + SHL64(bitrev(srcstep, VL) * EXTS(D), n)
     RT <- [0] * 56 || MEM(EA, 1)
     RA <- EA
 
@@ -41,7 +45,8 @@ SVD-Form
 Pseudo-code:
 
     b <- (RA|0)
-    EA <- b + (bitrev(srcstep, VL) * EXTS(D)) << RC
+    n <- (RC)[58:63]
+    EA <- b + SHL64(bitrev(srcstep, VL) * EXTS(D), n)
     RT <- [0] * 48 || MEM(EA, 2)
 
 Special Registers Altered:
@@ -56,7 +61,8 @@ SVD-Form
 
 Pseudo-code:
 
-    EA <- (RA) + (bitrev(srcstep, VL) * EXTS(D)) << RC
+    n <- (RC)[58:63]
+    EA <- (RA) + SHL64(bitrev(srcstep, VL) * EXTS(D), n)
     RT <- [0] * 48 || MEM(EA, 2)
     RA <- EA
 
@@ -73,7 +79,8 @@ SVD-Form
 Pseudo-code:
 
     b <- (RA|0)
-    EA <- b + (bitrev(srcstep, VL) * EXTS(D)) << RC
+    n <- (RC)[58:63]
+    EA <- b + SHL64(bitrev(srcstep, VL) * EXTS(D), n)
     RT <- EXTS(MEM(EA, 2))
 
 Special Registers Altered:
@@ -88,7 +95,8 @@ SVD-Form
 
 Pseudo-code:
 
-    EA <- (RA) + (bitrev(srcstep, VL) * EXTS(D)) << RC
+    n <- (RC)[58:63]
+    EA <- (RA) + SHL64(bitrev(srcstep, VL) * EXTS(D), n)
     RT <- EXTS(MEM(EA, 2))
     RA <- EA
 
@@ -105,7 +113,8 @@ SVD-Form
 Pseudo-code:
 
     b <- (RA|0)
-    EA <- b + (bitrev(srcstep, VL) * EXTS(D)) << RC
+    n <- (RC)[58:63]
+    EA <- b + SHL64(bitrev(srcstep, VL) * EXTS(D), n)
     RT <- [0] * 32 || MEM(EA, 4)
 
 Special Registers Altered:
@@ -120,7 +129,8 @@ SVD-Form
 
 Pseudo-code:
 
-    EA <- (RA) + (bitrev(srcstep, VL) * EXTS(D)) << RC
+    n <- (RC)[58:63]
+    EA <- (RA) + SHL64(bitrev(srcstep, VL) * EXTS(D), n)
     RT <- [0]*32 || MEM(EA, 4)
     RA <- EA
 
@@ -137,7 +147,8 @@ SVDS-Form
 Pseudo-code:
 
     b <- (RA|0)
-    EA <- b + (bitrev(srcstep, VL) * EXTS(DS || 0b00)) << RC
+    n <- (RC)[58:63]
+    EA <- b + SHL64(bitrev(srcstep, VL) * EXTS(DS || 0b00), n)
     RT <- EXTS(MEM(EA, 4))
 
 Special Registers Altered:
@@ -153,7 +164,8 @@ SVDS-Form
 Pseudo-code:
 
     b <- (RA|0)
-    EA <- b + (bitrev(srcstep, VL) * EXTS(DS || 0b00)) << RC
+    n <- (RC)[58:63]
+    EA <- b + SHL64(bitrev(srcstep, VL) * EXTS(DS || 0b00), n)
     RT <- MEM(EA, 8)
 
 Special Registers Altered:
@@ -168,7 +180,8 @@ SVDS-Form
 
 Pseudo-code:
 
-    EA <- (RA) + (bitrev(srcstep, VL) * EXTS(DS || 0b00)) << RC
+    n <- (RC)[58:63]
+    EA <- (RA) + SHL64(bitrev(srcstep, VL) * EXTS(DS || 0b00), n)
     RT <- MEM(EA, 8)
     RA <- EA