From: Michael Nolan <mtnolan2640@gmail.com>
Date: Fri, 8 May 2020 14:43:32 +0000 (-0400)
Subject: Add pipe data for ALU pipeline
X-Git-Tag: div_pipeline~1348
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=d8e082e66f158c0c8491c7bc434971947b84eaec;p=soc.git

Add pipe data for ALU pipeline
---

diff --git a/src/soc/alu/pipe_data.py b/src/soc/alu/pipe_data.py
new file mode 100644
index 00000000..e2231c85
--- /dev/null
+++ b/src/soc/alu/pipe_data.py
@@ -0,0 +1,27 @@
+from nmigen import Signal, Const
+from nmutil.dynamicpipe import SimpleHandshakeRedir
+from soc.alu.alu_input_record import CompALUOpSubset
+
+
+class ALUInitialData:
+
+    def __init__(self, pspec):
+        self.op = CompALUOpSubset()
+        self.a = Signal(64, reset_less=True)
+        self.b = Signal(64, reset_less=True)
+
+    def __iter__(self):
+        yield from self.op
+        yield self.a
+        yield self.b
+
+    def eq(self, i):
+        return [self.op.eq(i.op),
+                self.a.eq(i.a), self.b.eq(i.b)]
+
+
+
+
+class ALUPipeSpec:
+    def __init__(self):
+        self.pipekls = SimpleHandshakeRedir