From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Fri, 25 Mar 2022 17:37:03 +0000 (+0000)
Subject: fix attributes, sort out address
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=d8e53d10ab6510f2f45629dd92c25e0df16e7c6e;p=lambdasoc.git

fix attributes, sort out address
---

diff --git a/lambdasoc/periph/hyperram.py b/lambdasoc/periph/hyperram.py
index e0d54bd..446e495 100644
--- a/lambdasoc/periph/hyperram.py
+++ b/lambdasoc/periph/hyperram.py
@@ -16,11 +16,11 @@ Usage example when wiring up an external pmod.
 use platform.add_extension to first define the pins:
 
     from nmigen.resources.memory import HyperRAMResources
-    hyperram_ios = HyperRAMResources(cs_n="B1",
+    hyperram_ios = HyperRAMResources(cs="B1",
                                      dq="D0 D1 D2 D3 D4 D7 D6 D7",
                                      rwds="B2", rst_n="B3", ck_p="B4",
-                                     attrs=IOStandard("LVCMOS33"))
-    self.platform.add_extension(hyperram_ios)
+                                     attrs=Attrs(IOSTANDARD="LVCMOS33"))
+    self.platform.add_resources(hyperram_ios)
     io = self.platform.request("hyperram")
 
 this trick will work with the 1-IC HyperRAM PMOD by Piotr Esden, sold
@@ -198,7 +198,6 @@ class HyperRAM(Peripheral, Elaboratable):
             ca[47].eq(~self.bus.we),          # R/W#
             ca[45].eq(1),                     # Burst Type (Linear)
             ca[16:45].eq(self.bus.adr[la:]),  # Row & Upper Column Address
-            ca[1:3].eq(self.bus.adr[0:2]),    # Lower Column Address
             ca[ashift:3].eq(bus.adr),         # Lower Column Address
         ]