From: lkcl Date: Thu, 8 Sep 2022 16:31:30 +0000 (+0100) Subject: (no commit message) X-Git-Tag: opf_rfc_ls005_v1~607 X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=d8f731f04fe7d2c0183a1e84187a65597f870605;p=libreriscv.git --- diff --git a/openpower/sv/rfc/ls001.mdwn b/openpower/sv/rfc/ls001.mdwn index a7f3a0bc2..a08bce243 100644 --- a/openpower/sv/rfc/ls001.mdwn +++ b/openpower/sv/rfc/ls001.mdwn @@ -36,11 +36,13 @@ them. Therefore because the goal of RED Semiconductor Ltd, an OpenPOWER Stakeholder, is to bring to market mass-volume general-purpose compute processors that -are competitive in the 3D GPU Audio Visual DSP EDGE IoT markets, Simple-V +are competitive in the 3D GPU Audio Visual DSP EDGE IoT desktop +chromebook netbook smartphone laptop markets, Simple-V has to be accompanied by corresponding **Scalar** instructions that bring the **Scalar** Power ISA up-to-date. These include IEEE754 Transcendentals AV cryptographic Biginteger and bitmanipulation operations that ARM Intel -AMD and many other ISAs have been adding over the past 12 years. +AMD and many other ISAs have been adding over the past 12 years and Power ISA +has not. *Thus it becomes necesary to consider the Architectural Resource Allocation of not just Simple-V but the 80-100 Scalar instructions all at the same time*.