From: Richard Kenner Date: Fri, 20 Oct 1995 22:46:03 +0000 (-0400) Subject: (move_to_float insns): Change move_to_float so that it doesn't have a clobber of... X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=d904e9ed26fdf01cd9ba844de0563bab3ea79b3c;p=gcc.git (move_to_float insns): Change move_to_float so that it doesn't have a clobber of the memory address... (move_to_float insns): Change move_to_float so that it doesn't have a clobber of the memory address, and instead passes the stack temp's memory address as one of the unspec args. (fix_truncdfsi2): Use rs6000_stack_temp to allocate the temp. (multiply, shift insns): Fix all cases of multiply and shift insns so that the right mnemonics are used for -mcpu=common with both -m{old,new}-mnemonics. From-SVN: r10487 --- diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md index 7851358e081..f5ecb7ec255 100644 --- a/gcc/config/rs6000/rs6000.md +++ b/gcc/config/rs6000/rs6000.md @@ -1155,8 +1155,8 @@ (match_operand:SI 2 "reg_or_short_operand" "r,I")))] "! TARGET_POWER" "@ - mullw %0,%1,%2 - mulli %0,%1,%2" + {muls|mullw} %0,%1,%2 + {muli|mulli} %0,%1,%2" [(set_attr "type" "imul")]) (define_insn "" @@ -1177,7 +1177,7 @@ (const_int 0))) (clobber (match_scratch:SI 3 "=r"))] "! TARGET_POWER" - "mullw. %3,%1,%2" + "{muls.|mullw.} %3,%1,%2" [(set_attr "type" "delayed_compare")]) (define_insn "" @@ -1200,7 +1200,7 @@ (set (match_operand:SI 0 "gpc_reg_operand" "=r") (mult:SI (match_dup 1) (match_dup 2)))] "! TARGET_POWER" - "mullw. %0,%1,%2" + "{muls.|mullw.} %0,%1,%2" [(set_attr "type" "delayed_compare")]) ;; Operand 1 is divided by operand 2; quotient goes to operand @@ -2300,7 +2300,7 @@ (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r") (match_operand:SI 2 "reg_or_cint_operand" "ri")))] "! TARGET_POWER" - "slw%I2 %0,%1,%h2" + "{sl|slw}%I2 %0,%1,%h2" [(set_attr "length" "8")]) (define_insn "" @@ -2323,7 +2323,7 @@ (const_int 0))) (clobber (match_scratch:SI 3 "=r"))] "! TARGET_POWER" - "slw%I2. %3,%1,%h2" + "{sl|slw}%I2. %3,%1,%h2" [(set_attr "type" "delayed_compare")]) (define_insn "" @@ -2348,7 +2348,7 @@ (set (match_operand:SI 0 "gpc_reg_operand" "=r") (ashift:SI (match_dup 1) (match_dup 2)))] "! TARGET_POWER" - "slw%I2. %0,%1,%h2" + "{sl|slw}%I2. %0,%1,%h2" [(set_attr "type" "delayed_compare")]) (define_insn "" @@ -2415,7 +2415,7 @@ (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r") (match_operand:SI 2 "reg_or_cint_operand" "ri")))] "! TARGET_POWER" - "srw%I2 %0,%1,%h2") + "{sr|srw}%I2 %0,%1,%h2") (define_insn "" [(set (match_operand:CC 0 "cc_reg_operand" "=x,x") @@ -2437,7 +2437,7 @@ (const_int 0))) (clobber (match_scratch:SI 3 "=r"))] "! TARGET_POWER" - "srw%I2. %3,%1,%h2" + "{sr|srw}%I2. %3,%1,%h2" [(set_attr "type" "delayed_compare")]) (define_insn "" @@ -2462,7 +2462,7 @@ (set (match_operand:SI 0 "gpc_reg_operand" "=r") (lshiftrt:SI (match_dup 1) (match_dup 2)))] "! TARGET_POWER" - "srw%I2. %0,%1,%h2" + "{sr|srw}%I2. %0,%1,%h2" [(set_attr "type" "delayed_compare")]) (define_insn "" @@ -2627,7 +2627,7 @@ (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r") (match_operand:SI 2 "reg_or_cint_operand" "ri")))] "! TARGET_POWER" - "sraw%I2 %0,%1,%h2") + "{sra|sraw}%I2 %0,%1,%h2") (define_insn "" [(set (match_operand:CC 0 "cc_reg_operand" "=x,x") @@ -2649,7 +2649,7 @@ (const_int 0))) (clobber (match_scratch:SI 3 "=r"))] "! TARGET_POWER" - "sraw%I2. %3,%1,%h2" + "{sra|sraw}%I2. %3,%1,%h2" [(set_attr "type" "delayed_compare")]) (define_insn "" @@ -2674,7 +2674,7 @@ (set (match_operand:SI 0 "gpc_reg_operand" "=r") (ashiftrt:SI (match_dup 1) (match_dup 2)))] "! TARGET_POWER" - "sraw%I2. %0,%1,%h2" + "{sra|sraw}%I2. %0,%1,%h2" [(set_attr "type" "delayed_compare")]) ;; Floating-point insns, excluding normal data motion. @@ -3362,47 +3362,50 @@ }") (define_expand "move_to_float" - [(parallel [(set (match_operand:DF 0 "gpc_reg_operand" "") - (unspec [(match_operand:SI 1 "gpc_reg_operand" "") - (match_operand:SI 2 "gpc_reg_operand" "")] 2)) - (clobber (match_dup 3))])] + [(set (match_operand:DF 0 "gpc_reg_operand" "") + (unspec [(match_operand:SI 1 "gpc_reg_operand" "") + (match_operand:SI 2 "gpc_reg_operand" "") + (match_dup 3)] 2))] "! TARGET_POWERPC64 && TARGET_HARD_FLOAT" " { - if (float_conv_temp == NULL_RTX) - { - float_conv_temp = assign_stack_local (DFmode, 8, 0); - if (!offsettable_mem_operand (float_conv_temp, DFmode)) - XEXP (float_conv_temp, 0) = copy_addr_to_reg (XEXP (float_conv_temp, 0)); - } - - operands[3] = float_conv_temp; + operands[3] = XEXP (rs6000_stack_temp (DFmode, 8, 1), 0); }") (define_split [(set (match_operand:DF 0 "gpc_reg_operand" "") (unspec [(match_operand:SI 1 "gpc_reg_operand" "") - (match_operand:SI 2 "gpc_reg_operand" "")] 2)) - (clobber (match_operand:DF 3 "offsettable_mem_operand" ""))] + (match_operand:SI 2 "gpc_reg_operand" "") + (match_operand:SI 3 "offsettable_addr_operand" "")] 2))] "reload_completed" [(set (match_dup 4) (match_dup 1)) (set (match_dup 5) (match_dup 2)) - (set (match_dup 0) (match_dup 3))] + (set (match_dup 0) (mem:DF (match_dup 3)))] " { - int little = (WORDS_BIG_ENDIAN == 0); - operands[4] = operand_subword (operands[3], 1 - little, 0, DFmode); - operands[5] = operand_subword (operands[3], little, 0, DFmode); + rtx word1 = gen_rtx (MEM, SImode, operands[3]); + rtx word2 = gen_rtx (MEM, SImode, plus_constant (operands[3], 4)); - MEM_IN_STRUCT_P (operands[4]) = 1; - MEM_IN_STRUCT_P (operands[5]) = 1; + MEM_IN_STRUCT_P (word1) = 1; + MEM_IN_STRUCT_P (word2) = 1; + + if (WORDS_BIG_ENDIAN) + { + operands[4] = word2; + operands[5] = word1; + } + else + { + operands[4] = word1; + operands[5] = word2; + } }") (define_insn "" [(set (match_operand:DF 0 "gpc_reg_operand" "=f") (unspec [(match_operand:SI 1 "gpc_reg_operand" "r") - (match_operand:SI 2 "gpc_reg_operand" "r")] 2)) - (clobber (match_operand:DF 3 "offsettable_mem_operand" "=o"))] + (match_operand:SI 2 "gpc_reg_operand" "r") + (match_operand:SI 3 "offsettable_addr_operand" "p")] 2))] "! TARGET_POWERPC64 && TARGET_HARD_FLOAT" "#" [(set_attr "length" "12")]) @@ -3416,7 +3419,7 @@ if (TARGET_POWER2 || TARGET_POWERPC) { int endian = (WORDS_BIG_ENDIAN == 0); - rtx stack_slot = assign_stack_temp (DImode, 8, 0); + rtx stack_slot = rs6000_stack_temp (DImode, 8, 1); rtx temp = gen_reg_rtx (DImode); emit_insn (gen_fpcvtsi (temp, operands[1])); @@ -3608,12 +3611,13 @@ { if (! TARGET_POWER && ! TARGET_POWERPC) { + int endian = (WORDS_BIG_ENDIAN == 0); emit_move_insn (gen_rtx (REG, SImode, 3), operands[1]); emit_move_insn (gen_rtx (REG, SImode, 4), operands[2]); emit_insn (gen_mull_call ()); - emit_move_insn (operand_subword (operands[0], 0, 0, DImode), + emit_move_insn (operand_subword (operands[0], endian, 0, DImode), gen_rtx (REG, SImode, 3)); - emit_move_insn (operand_subword (operands[0], 1, 0, DImode), + emit_move_insn (operand_subword (operands[0], 1 - endian, 0, DImode), gen_rtx (REG, SImode, 4)); DONE; }