From: Nanley Chery <nanley.g.chery@intel.com>
Date: Thu, 9 May 2019 23:38:12 +0000 (-0700)
Subject: intel/blorp: Halve the Gen12 fast-clear/resolve rectangle
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=d90bffaef8b0ff3bc8736a1ac30afe7390eeac29;p=mesa.git

intel/blorp: Halve the Gen12 fast-clear/resolve rectangle

Update their dimensions according to the Bspec.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
---

diff --git a/src/intel/blorp/blorp_clear.c b/src/intel/blorp/blorp_clear.c
index 595bac18e61..4c33fa2a372 100644
--- a/src/intel/blorp/blorp_clear.c
+++ b/src/intel/blorp/blorp_clear.c
@@ -232,10 +232,12 @@ get_fast_clear_rect(const struct isl_device *dev,
 
       x_align *= 16;
 
-      /* SKL+ line alignment requirement for Y-tiled are half those of the prior
-       * generations.
+      /* The line alignment requirement for Y-tiled is halved at SKL and again
+       * at TGL.
        */
-      if (dev->info->gen >= 9)
+      if (dev->info->gen >= 12)
+         y_align *= 8;
+      else if (dev->info->gen >= 9)
          y_align *= 16;
       else
          y_align *= 32;
@@ -990,7 +992,10 @@ blorp_ccs_resolve(struct blorp_batch *batch,
    assert(aux_fmtl->txc == ISL_TXC_CCS);
 
    unsigned x_scaledown, y_scaledown;
-   if (ISL_DEV_GEN(batch->blorp->isl_dev) >= 9) {
+   if (ISL_DEV_GEN(batch->blorp->isl_dev) >= 12) {
+      x_scaledown = aux_fmtl->bw * 8;
+      y_scaledown = aux_fmtl->bh * 4;
+   } else if (ISL_DEV_GEN(batch->blorp->isl_dev) >= 9) {
       x_scaledown = aux_fmtl->bw * 8;
       y_scaledown = aux_fmtl->bh * 8;
    } else if (ISL_DEV_GEN(batch->blorp->isl_dev) >= 8) {