From: Andrew Zonenberg <azonenberg@drawersteak.com>
Date: Thu, 21 Apr 2016 03:48:19 +0000 (-0700)
Subject: Added GP_VREF cell
X-Git-Tag: yosys-0.7~255
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=d90c1e952256dc00d070863835e061d73e4bc6b3;p=yosys.git

Added GP_VREF cell
---

diff --git a/techlibs/greenpak4/cells_sim.v b/techlibs/greenpak4/cells_sim.v
index 554e2e13f..40d79aeae 100644
--- a/techlibs/greenpak4/cells_sim.v
+++ b/techlibs/greenpak4/cells_sim.v
@@ -263,6 +263,12 @@ module GP_VDD(output OUT);
        assign OUT = 1;
 endmodule
 
+module GP_VREF(input VIN, output reg VOUT);
+	parameter VIN_DIV = 1;
+	parameter VREF = 0;
+	//cannot simulate mixed signal IP
+endmodule
+
 module GP_VSS(output OUT);
        assign OUT = 0;
 endmodule