From: Michael Nolan Date: Fri, 8 May 2020 17:56:37 +0000 (-0400) Subject: Add and or and xor to main_stage X-Git-Tag: div_pipeline~1337 X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=d92def51d11537f9589232b697de4febd1516fea;p=soc.git Add and or and xor to main_stage --- diff --git a/src/soc/alu/formal/proof_main_stage.py b/src/soc/alu/formal/proof_main_stage.py index 372cf993..11d2c61d 100644 --- a/src/soc/alu/formal/proof_main_stage.py +++ b/src/soc/alu/formal/proof_main_stage.py @@ -59,9 +59,16 @@ class Driver(Elaboratable): dut_sig = getattr(dut.o.ctx.op, name) comb += Assert(dut_sig == rec_sig) - with m.If(rec.insn_type == InternalOp.OP_ADD): - comb += Assert(Cat(dut.o.o, dut.o.carry_out) == - (a + b + carry_in)) + with m.Switch(rec.insn_type): + with m.Case(InternalOp.OP_ADD): + comb += Assert(Cat(dut.o.o, dut.o.carry_out) == + (a + b + carry_in)) + with m.Case(InternalOp.OP_AND): + comb += Assert(dut.o.o == a & b) + with m.Case(InternalOp.OP_OR): + comb += Assert(dut.o.o == a | b) + with m.Case(InternalOp.OP_XOR): + comb += Assert(dut.o.o == a ^ b) return m diff --git a/src/soc/alu/main_stage.py b/src/soc/alu/main_stage.py index d443e977..615a7845 100644 --- a/src/soc/alu/main_stage.py +++ b/src/soc/alu/main_stage.py @@ -27,6 +27,12 @@ class ALUMainStage(PipeModBase): with m.Case(InternalOp.OP_ADD): comb += self.o.o.eq(add_output[0:64]) comb += self.o.carry_out.eq(add_output[64]) + with m.Case(InternalOp.OP_AND): + comb += self.o.o.eq(self.i.a & self.i.b) + with m.Case(InternalOp.OP_OR): + comb += self.o.o.eq(self.i.a | self.i.b) + with m.Case(InternalOp.OP_XOR): + comb += self.o.o.eq(self.i.a ^ self.i.b) comb += self.o.ctx.eq(self.i.ctx)