From: Clifford Wolf <clifford@clifford.at>
Date: Sat, 8 Nov 2014 11:38:48 +0000 (+0100)
Subject: Added missing fixup_ports() calls to "rename" command
X-Git-Tag: yosys-0.5~283
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=d92fb5b35eff8c616f1b5de355d13b642e830c8f;p=yosys.git

Added missing fixup_ports() calls to "rename" command
---

diff --git a/passes/cmds/rename.cc b/passes/cmds/rename.cc
index 1006686ef..b2e10e557 100644
--- a/passes/cmds/rename.cc
+++ b/passes/cmds/rename.cc
@@ -36,6 +36,8 @@ static void rename_in_module(RTLIL::Module *module, std::string from_name, std::
 		if (it.first == from_name) {
 			log("Renaming wire %s to %s in module %s.\n", log_id(it.second), log_id(to_name), log_id(module));
 			module->rename(it.second, to_name);
+			if (it.second->port_id)
+				module->fixup_ports();
 			return;
 		}
 
@@ -124,6 +126,7 @@ struct RenamePass : public Pass {
 					new_wires[it.second->name] = it.second;
 				}
 				module->wires_.swap(new_wires);
+				module->fixup_ports();
 
 				std::map<RTLIL::IdString, RTLIL::Cell*> new_cells;
 				for (auto &it : module->cells_) {
@@ -154,6 +157,7 @@ struct RenamePass : public Pass {
 					new_wires[it.second->name] = it.second;
 				}
 				module->wires_.swap(new_wires);
+				module->fixup_ports();
 
 				std::map<RTLIL::IdString, RTLIL::Cell*> new_cells;
 				for (auto &it : module->cells_) {