From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Tue, 20 Sep 2022 20:27:33 +0000 (+0100)
Subject: sv.bc reclassified as RM-2P-1S by eliminating SPRs.
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=d9327481424b73cf71034983b3f75083180d39b9;p=openpower-isa.git

sv.bc reclassified as RM-2P-1S by eliminating SPRs.
strictly it should be RM-1P-1S but there is a bug. needs investigation.
sv_analysis temporarily classifies as twin predication for now
---

diff --git a/openpower/isatables/RM-2P-1S.csv b/openpower/isatables/RM-2P-1S.csv
new file mode 100644
index 00000000..dee438fe
--- /dev/null
+++ b/openpower/isatables/RM-2P-1S.csv
@@ -0,0 +1,3 @@
+insn,mode,CONDITIONS,Ptype,Etype,SM,0,1,2,3,in1,in2,in3,out,CR in,CR out,out2
+bc,BRANCH,,2P,EXTRA3,NO,s:BI,0,0,0,0,0,0,0,BI,0,0
+bclr,BRANCH,,2P,EXTRA3,NO,s:BI,0,0,0,0,0,0,0,BI,0,0
diff --git a/openpower/isatables/RM-2P-1S1D.csv b/openpower/isatables/RM-2P-1S1D.csv
index 14bfc59a..1c0a2f8f 100644
--- a/openpower/isatables/RM-2P-1S1D.csv
+++ b/openpower/isatables/RM-2P-1S1D.csv
@@ -1,9 +1,7 @@
 insn,mode,CONDITIONS,Ptype,Etype,SM,0,1,2,3,in1,in2,in3,out,CR in,CR out,out2
 mcrf,NORMAL,,2P,EXTRA3,EN,d:BF,s:BFA,0,0,0,0,0,0,BFA,BF,0
-bclr,BRANCH,,2P,EXTRA3,EN,d:BI,s:BI,0,0,SPR,SPR,0,SPR,BI,0,0
 mfcr/mfocrf,NORMAL,,2P,EXTRA3,EN,d:RT,s:CR,0,0,0,0,0,RT,WHOLE_REG,0,0
 setb,NORMAL,,2P,EXTRA3,EN,d:RT,s:BFA,0,0,0,0,0,RT,BFA,0,0
-bc,BRANCH,,2P,EXTRA3,EN,d:BI,s:BI,0,0,SPR,0,0,SPR,BI,0,0
 5/0=ftsqrt,NORMAL,,2P,EXTRA3,EN,d:BF,s:FRB,0,0,0,FRB,0,0,0,BF,0
 22/7=mtfsf,NORMAL,,2P,EXTRA3,EN,d:CR1,s:FRB,0,0,0,FRB,0,0,0,CR1,0
 cmpli,NORMAL,,2P,EXTRA3,EN,d:BF,s:RA,0,0,RA,0,0,0,0,BF,0
diff --git a/src/openpower/sv/sv_analysis.py b/src/openpower/sv/sv_analysis.py
index 8cc0833d..c1edc668 100644
--- a/src/openpower/sv/sv_analysis.py
+++ b/src/openpower/sv/sv_analysis.py
@@ -314,13 +314,21 @@ def read_csvs():
                 continue  # skip pseudo-alias lxxxbr
             if insn_name in ['mcrxr', 'mcrxrx', 'darn']:
                 continue
-            if insn_name in ['bctar', 'bcctr']:
+            if insn_name in ['bctar', 'bcctr']: # for now. TODO
                 continue
             if 'rfid' in insn_name:
                 continue
             if 'addpcis' in insn_name: # skip for now
                 continue
 
+            # sv.bc is being classified as 2P-2S-1D by mistake due to SPRs
+            if insn_name.startswith('bc'):
+                # whoops: remove out reg (SPRs CTR etc)
+                row['in1'] = 'NONE'
+                row['in2'] = 'NONE'
+                row['in3'] = 'NONE'
+                row['out'] = 'NONE'
+
             insns[(insn_name, condition)] = row  # accumulate csv data
             insn_to_csv[insn_name] = csvname_  # CSV file name by instruction
             dkey = create_key(row)
@@ -512,9 +520,6 @@ def extra_classifier(insn_name, value, name, res, regs):
         elif regs == ['', 'FRB', '', 'FRT', '', 'CR1']:
             res['0'] = 'd:FRT;d:CR1'  # FRT,CR1: Rdest1_EXTRA3
             res['1'] = 's:FRB'  # FRB: Rsrc1_EXTRA3
-        elif insn_name.startswith('bc'):
-            res['0'] = 'd:BI'  # BI: Rdest1_EXTRA3
-            res['1'] = 's:BI'  # BI: Rsrc1_EXTRA3
         elif insn_name == 'fishmv':
             # an overwrite instruction
             res['0'] = 'd:FRS'  # FRS: Rdest1_EXTRA3
@@ -615,6 +620,12 @@ def extra_classifier(insn_name, value, name, res, regs):
         if insn_name == 'fmvis':
             res['0'] = 'd:FRS'  # FRS: Rdest1_EXTRA3
 
+    # HACK! thos should be RM-1P-1S butvthere is a bug with sv.bc
+    elif value == 'RM-2P-1S':
+        res['Etype'] = 'EXTRA3'  # RM EXTRA3 type
+        if insn_name.startswith('bc'):
+            res['0'] = 's:BI'  # BI: Rsrc1_EXTRA3
+
 
 def process_csvs(format):
 
@@ -650,7 +661,7 @@ def process_csvs(format):
               '1W-CRi': 'RM-2P-1S1D',
               'CRio': 'RM-2P-1S1D',
               'CR=2R1W': 'RM-1P-2S1D',
-              'CRi': 'non-SV',
+              'CRi': 'RM-2P-1S', # HACK, bc here, it should be 1P
               'imm': 'non-SV',
               '': 'non-SV',
               'LDST-2R-imm': 'LDSTRM-2P-2S',