From: lkcl <lkcl@web>
Date: Sun, 5 Sep 2021 16:24:45 +0000 (+0100)
Subject: (no commit message)
X-Git-Tag: DRAFT_SVP64_0_1~218
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=d937dd083477fbff90c61d277086526fa80d3c28;p=libreriscv.git

---

diff --git a/openpower/sv/ldst.mdwn b/openpower/sv/ldst.mdwn
index 1d56ac9a4..1baca3102 100644
--- a/openpower/sv/ldst.mdwn
+++ b/openpower/sv/ldst.mdwn
@@ -27,7 +27,7 @@ Vector Operations, then in order to keep the ALUs 100% occupied the
 Memory infrastructure (and the ISA itself) correspondingly needs Vector
 Memory Operations as well.
 
-Vectorised Load and Store also presents an extra dimension (literslly)
+Vectorised Load and Store also presents an extra dimension (literally)
 which creates scenarios unique to Vector applications, that a Scalar
 (and even a SIMD) ISA simply never encounters.  SVP64 endeavours to
 add such modes without changing the behaviour of the underlying Base