From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Thu, 10 Feb 2022 12:37:39 +0000 (+0000)
Subject: resolve imports, whitespace, add Copyright
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=d93e308b123be49853b2b276675d7452893cfe09;p=ls2.git

resolve imports, whitespace, add Copyright
---

diff --git a/examples/crg.py b/examples/crg.py
index f5d35d3..3e3b432 100644
--- a/examples/crg.py
+++ b/examples/crg.py
@@ -1,11 +1,18 @@
-# This file is Copyright (c) 2020 LambdaConcept <contact@lambdaconcept.com>
+# Copyright (c) 2020 LambdaConcept <contact@lambdaconcept.com>
+# Copyright (c) 2021 Luke Kenneth Casson Leighton <lkcl@lkcl.net>
 
-from nmigen import *
+
+from nmigen import (Elaboratable, Instance, Signal, ClockDomain,
+                    ClockSignal, ResetSignal)
 
 __ALL__ = ["ECPIX5CRG"]
 
+
 class PLL(Elaboratable):
-    def __init__(self, clkin, clksel=Signal(shape=2, reset=2), clkout1=Signal(), clkout2=Signal(), clkout3=Signal(), clkout4=Signal(), lock=Signal(), CLKI_DIV=1, CLKFB_DIV=2, CLK1_DIV=3, CLK2_DIV=24):
+    def __init__(self, clkin, clksel=Signal(shape=2, reset=2),
+                        clkout1=Signal(), clkout2=Signal(),
+                        clkout3=Signal(), clkout4=Signal(), lock=Signal(),
+                        CLKI_DIV=1, CLKFB_DIV=2, CLK1_DIV=3, CLK2_DIV=24):
         self.clkin = clkin
         self.clkout1 = clkout1
         self.clkout2 = clkout2
@@ -88,8 +95,10 @@ class ECPIX5CRG(Elaboratable):
         gsr1 = Signal()
 
         m.submodules += [
-            Instance("FD1S3AX", p_GSR="DISABLED", i_CK=ClockSignal("rawclk"), i_D=~reset, o_Q=gsr0),
-            Instance("FD1S3AX", p_GSR="DISABLED", i_CK=ClockSignal("rawclk"), i_D=gsr0,   o_Q=gsr1),
+            Instance("FD1S3AX", p_GSR="DISABLED", i_CK=ClockSignal("rawclk"),
+                     i_D=~reset, o_Q=gsr0),
+            Instance("FD1S3AX", p_GSR="DISABLED", i_CK=ClockSignal("rawclk"),
+                     i_D=gsr0,   o_Q=gsr1),
             Instance("SGSR", i_CLK=ClockSignal("rawclk"), i_GSR=gsr1),
         ]
 
@@ -102,12 +111,16 @@ class ECPIX5CRG(Elaboratable):
 
         # Generating sync2x (200Mhz) and init (25Mhz) from clk100
         cd_sync2x = ClockDomain("sync2x", local=False)
-        cd_sync2x_unbuf = ClockDomain("sync2x_unbuf", local=False, reset_less=True)
+        cd_sync2x_unbuf = ClockDomain("sync2x_unbuf", local=False,
+                     reset_less=True)
         cd_init = ClockDomain("init", local=False)
         cd_sync = ClockDomain("sync", local=False)
         cd_dramsync = ClockDomain("dramsync", local=False)
-        m.submodules.pll = pll = PLL(ClockSignal("rawclk"), CLKI_DIV=1, CLKFB_DIV=2, CLK1_DIV=3, CLK2_DIV=24,
-            clkout1=ClockSignal("sync2x_unbuf"), clkout2=ClockSignal("init"))
+        m.submodules.pll = pll = PLL(ClockSignal("rawclk"),
+                                     CLKI_DIV=1, CLKFB_DIV=2,
+                                     CLK1_DIV=3, CLK2_DIV=24,
+                                     clkout1=ClockSignal("sync2x_unbuf"),
+                                     clkout2=ClockSignal("init"))
         m.submodules += Instance("ECLKSYNCB",
                 i_ECLKI = ClockSignal("sync2x_unbuf"),
                 i_STOP  = 0,
@@ -122,7 +135,7 @@ class ECPIX5CRG(Elaboratable):
         m.d.comb += ResetSignal("dramsync").eq(~pll.lock|~pod_done)
 
         # # Generating sync (100Mhz) from sync2x
-        
+
         m.submodules += Instance("CLKDIVF",
             p_DIV="2.0",
             i_ALIGNWD=0,