From: Kajoljain379 <kajoljain797@gmail.com>
Date: Wed, 10 Apr 2019 05:40:49 +0000 (+0000)
Subject: arch-power: Added dcbz instruction
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=d940b4dde1ef7dd34c6fac5379cc6334d0d06d4b;p=gem5.git

arch-power: Added dcbz instruction

* Added dcbz cache instruction which used by kernel to clear multiple
  words at a time.

Change-Id: I7cfd7c93cac2d4419db987e7cf8fef8b4c71f805
Signed-off-by: Kajoljain379 <kajoljain797@gmail.com>
---

diff --git a/src/arch/power/isa/decoder.isa b/src/arch/power/isa/decoder.isa
index c73df0b38..9e0fc3c9e 100644
--- a/src/arch/power/isa/decoder.isa
+++ b/src/arch/power/isa/decoder.isa
@@ -964,6 +964,21 @@ decode PO default Unknown::unknown() {
         format MiscOp {
             278: dcbt({{ }});
             246: dcbtst({{ }});
+
+            1014: dcbz({{
+                  Request::Flags flags = Request::PHYSICAL;
+                  Addr EA;
+                  if(RA == 0)
+                    EA = Rb & -128ULL;
+                  else
+                    EA = (Ra + Rb) & -128ULL;
+                  Mem = 0;
+                  for (int i = 0; i < 16; ++i) {
+                    writeMemAtomic(xc, traceData, Mem,EA + i*8,
+                                            flags, NULL);
+                }
+            }});
+
             86: dcbf({{ }});
             598: sync({{ }}, [ IsMemBarrier ]);
             854: eieio({{ }}, [ IsMemBarrier ]);