From: Will Schmidt <will_schmidt@vnet.ibm.com>
Date: Thu, 11 Oct 2018 21:10:12 +0000 (+0000)
Subject: fold-vec-select-char.c: New.
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=d9519daf1e1632872c28c45996e4849665b9854e;p=gcc.git

fold-vec-select-char.c: New.

[testsuite]

2018-10-11  Will Schmidt  <will_schmidt@vnet.ibm.com>

	* gcc.target/powerpc/fold-vec-select-char.c: New.
	* gcc.target/powerpc/fold-vec-select-double.c: New.
	* gcc.target/powerpc/fold-vec-select-float.c: New.
	* gcc.target/powerpc/fold-vec-select-int.c: New.
	* gcc.target/powerpc/fold-vec-select-longlong.c: New.
	* gcc.target/powerpc/fold-vec-select-short.c: New.

From-SVN: r265065
---

diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog
index c8d0d3fbd35..ebc684a7575 100644
--- a/gcc/testsuite/ChangeLog
+++ b/gcc/testsuite/ChangeLog
@@ -1,3 +1,12 @@
+2018-10-11  Will Schmidt  <will_schmidt@vnet.ibm.com>
+
+	* gcc.target/powerpc/fold-vec-select-char.c: New.
+	* gcc.target/powerpc/fold-vec-select-double.c: New.
+	* gcc.target/powerpc/fold-vec-select-float.c: New.
+	* gcc.target/powerpc/fold-vec-select-int.c: New.
+	* gcc.target/powerpc/fold-vec-select-longlong.c: New.
+	* gcc.target/powerpc/fold-vec-select-short.c: New.
+
 2018-10-09  Giuliano Belinassi  <giuliano.belinassi@usp.br>
 
 	PR tree-optimization/86829
@@ -5,6 +14,15 @@
 	* gcc.dg/sinatan-2.c: New test.
 	* gcc.dg/sinatan-3.c: New test.
 
+2018-10-11  Will Schmidt  <will_schmidt@vnet.ibm.com>
+
+	* gcc.target/powerpc/fold-vec-select-char.c: New.
+	* gcc.target/powerpc/fold-vec-select-double.c: New.
+	* gcc.target/powerpc/fold-vec-select-float.c: New.
+	* gcc.target/powerpc/fold-vec-select-int.c: New.
+	* gcc.target/powerpc/fold-vec-select-longlong.c: New.
+	* gcc.target/powerpc/fold-vec-select-short.c: New.
+
 2018-10-11  Will Schmidt  <will_schmidt@vnet.ibm.com>
 
 	* gcc.target/powerpc/fold-vec-mergeeo-floatdouble.c: New.
diff --git a/gcc/testsuite/gcc.target/powerpc/fold-vec-select-char.c b/gcc/testsuite/gcc.target/powerpc/fold-vec-select-char.c
new file mode 100644
index 00000000000..e055c017536
--- /dev/null
+++ b/gcc/testsuite/gcc.target/powerpc/fold-vec-select-char.c
@@ -0,0 +1,46 @@
+/* Verify that overloaded built-ins for vec_sel with char
+   inputs produce the right code.  */
+
+/* { dg-do compile } */
+/* { dg-require-effective-target powerpc_vsx_ok } */
+/* { dg-options "-maltivec -O2" } */
+
+#include <altivec.h>
+
+vector bool char
+test1_0 (vector bool char x, vector bool char y, vector bool char z)
+{
+  return vec_sel (x, y, z);
+}
+
+vector bool char
+test1_1 (vector bool char x,vector bool char y, vector unsigned char z)
+{
+  return vec_sel (x, y, z);
+}
+
+vector signed char
+test3_0 (vector signed char x,vector signed char y, vector bool char  z)
+{
+  return vec_sel (x, y, z);
+}
+
+vector signed char
+test3_1 (vector signed char x,vector signed char  y, vector unsigned char z)
+{
+  return vec_sel (x, y, z);
+}
+
+vector unsigned char
+test6_0 (vector unsigned char x,vector unsigned char  y,vector bool char  z)
+{
+  return vec_sel (x, y, z);
+}
+
+vector unsigned char
+test6_1 (vector unsigned char x,vector unsigned char  y, vector unsigned char z)
+{
+  return vec_sel (x, y, z);
+}
+
+/* { dg-final { scan-assembler-times {\mxxsel\M|\mvsel\M} 6 } } */
diff --git a/gcc/testsuite/gcc.target/powerpc/fold-vec-select-double.c b/gcc/testsuite/gcc.target/powerpc/fold-vec-select-double.c
new file mode 100644
index 00000000000..b0969774f2f
--- /dev/null
+++ b/gcc/testsuite/gcc.target/powerpc/fold-vec-select-double.c
@@ -0,0 +1,23 @@
+/* Verify that overloaded built-ins for vec_sel with 
+   double inputs for VSX produce the right code.  */
+
+/* { dg-do compile { target { powerpc*-*-linux* } } } */
+/* { dg-require-effective-target powerpc_p8vector_ok } */
+/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power8" } } */
+/* { dg-options "-mcpu=power8 -O2" } */
+
+#include <altivec.h>
+
+vector double
+test2_0 (vector double x, vector double y, vector bool long long z)
+{
+  return vec_sel (x, y, z);
+}
+
+vector double
+test2_1 (vector double x, vector double y, vector unsigned long long z)
+{
+  return vec_sel (x, y, z);
+}
+
+/* { dg-final { scan-assembler-times "xxsel" 2 } } */
diff --git a/gcc/testsuite/gcc.target/powerpc/fold-vec-select-float.c b/gcc/testsuite/gcc.target/powerpc/fold-vec-select-float.c
new file mode 100644
index 00000000000..cc37eb59724
--- /dev/null
+++ b/gcc/testsuite/gcc.target/powerpc/fold-vec-select-float.c
@@ -0,0 +1,22 @@
+/* Verify that overloaded built-ins for vec_sel with float 
+   inputs for VSX produce the right code.  */
+
+/* { dg-do compile { target { powerpc*-*-linux* } } } */
+/* { dg-require-effective-target powerpc_vsx_ok } */
+/* { dg-options "-maltivec -O2" } */
+
+#include <altivec.h>
+
+vector float
+test1_0 (vector float x, vector float y, vector bool int z)
+{
+  return vec_sel (x, y, z);
+}
+
+vector float
+test1_1 (vector float x, vector float y, vector unsigned int z)
+{
+  return vec_sel (x, y, z);
+}
+
+/* { dg-final { scan-assembler-times {\mxxsel\M|\mvsel\M} 2 } } */
diff --git a/gcc/testsuite/gcc.target/powerpc/fold-vec-select-int.c b/gcc/testsuite/gcc.target/powerpc/fold-vec-select-int.c
new file mode 100644
index 00000000000..510fc564370
--- /dev/null
+++ b/gcc/testsuite/gcc.target/powerpc/fold-vec-select-int.c
@@ -0,0 +1,46 @@
+/* Verify that overloaded built-ins for vec_sel with int
+   inputs produce the right code.  */
+
+/* { dg-do compile } */
+/* { dg-require-effective-target powerpc_vsx_ok } */
+/* { dg-options "-maltivec -O2" } */
+
+#include <altivec.h>
+
+vector bool int
+test1_0 (vector bool int x, vector bool int y, vector bool int z)
+{
+  return vec_sel (x, y, z);
+}
+
+vector bool int
+test1_1 (vector bool int x, vector bool int y, vector unsigned int z)
+{
+  return vec_sel (x, y, z);
+}
+
+vector signed int
+test3_0 (vector signed int x, vector signed int y, vector bool int z)
+{
+  return vec_sel (x, y, z);
+}
+
+vector signed int
+test3_1 (vector signed int x, vector signed int y, vector unsigned int z)
+{
+  return vec_sel (x, y, z);
+}
+
+vector unsigned int
+test6_0 (vector unsigned int x, vector unsigned int y, vector bool int z)
+{
+  return vec_sel (x, y, z);
+}
+
+vector unsigned int
+test6_1 (vector unsigned int x, vector unsigned int y, vector unsigned int z)
+{
+  return vec_sel (x, y, z);
+}
+
+/* { dg-final { scan-assembler-times {\mxxsel\M|\mvsel\M} 6 } } */
diff --git a/gcc/testsuite/gcc.target/powerpc/fold-vec-select-longlong.c b/gcc/testsuite/gcc.target/powerpc/fold-vec-select-longlong.c
new file mode 100644
index 00000000000..449c0f0fda8
--- /dev/null
+++ b/gcc/testsuite/gcc.target/powerpc/fold-vec-select-longlong.c
@@ -0,0 +1,34 @@
+/* Verify that overloaded built-ins for vec_sel with long long
+   inputs produce the right code.  */
+
+/* { dg-do compile } */
+/* { dg-require-effective-target powerpc_vsx_ok } */
+/* { dg-options "-mvsx -O2" } */
+
+#include <altivec.h>
+
+vector bool long long
+test1_0 (vector bool long long x,vector bool long long y, vector bool long long z)
+{
+  return vec_sel (x, y, z);
+}
+
+vector bool long long
+test1_1 (vector bool long long x, vector bool long long y, vector unsigned long long z)
+{
+  return vec_sel (x, y, z);
+}
+
+vector signed long long
+test3_0 (vector signed long long x, vector signed long long y, vector bool long long z)
+{
+  return vec_sel (x, y, z);
+}
+
+vector unsigned long long
+test3_1 (vector unsigned long long x, vector unsigned long long y, vector bool long long z)
+{
+  return vec_sel (x, y, z);
+}
+
+/* { dg-final { scan-assembler-times "xxsel" 4 } } */
diff --git a/gcc/testsuite/gcc.target/powerpc/fold-vec-select-short.c b/gcc/testsuite/gcc.target/powerpc/fold-vec-select-short.c
new file mode 100644
index 00000000000..0d11fce81b2
--- /dev/null
+++ b/gcc/testsuite/gcc.target/powerpc/fold-vec-select-short.c
@@ -0,0 +1,46 @@
+/* Verify that overloaded built-ins for vec_sel with short
+   inputs produce the right code.  */
+
+/* { dg-do compile } */
+/* { dg-require-effective-target powerpc_vsx_ok } */
+/* { dg-options "-maltivec -O2" } */
+
+#include <altivec.h>
+
+vector bool short
+test1_0 (vector bool short x, vector bool short y, vector bool short z)
+{
+  return vec_sel (x, y, z);
+}
+
+vector bool short
+test1_1 (vector bool short x, vector bool short y, vector unsigned short z)
+{
+  return vec_sel (x, y, z);
+}
+
+vector signed short
+test3_0 (vector signed short x, vector signed short y, vector bool short z)
+{
+  return vec_sel (x, y, z);
+}
+
+vector signed short
+test3_1 (vector signed short x, vector signed short y, vector unsigned short z)
+{
+  return vec_sel (x, y, z);
+}
+
+vector unsigned short
+test6_0 (vector unsigned short x, vector unsigned short y, vector bool short z)
+{
+  return vec_sel (x, y, z);
+}
+
+vector unsigned short
+test6_1 (vector unsigned short x, vector unsigned short y, vector unsigned short z)
+{
+  return vec_sel (x, y, z);
+}
+
+/* { dg-final { scan-assembler-times {\mxxsel\M|\mvsel\M} 6 } } */