From: lkcl <lkcl@web>
Date: Sun, 21 Aug 2022 11:01:33 +0000 (+0100)
Subject: (no commit message)
X-Git-Tag: opf_rfc_ls005_v1~815
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=d95f6f2dc81ee124a23d9cfcd7775c561f39f64d;p=libreriscv.git

---

diff --git a/openpower/sv/ldst.mdwn b/openpower/sv/ldst.mdwn
index b45cef665..0f65bd84c 100644
--- a/openpower/sv/ldst.mdwn
+++ b/openpower/sv/ldst.mdwn
@@ -77,7 +77,13 @@ an alternative table meaning for [[sv/svp64]] mode.  The following modes make se
 
 More than that however it is necessary to fit the usual Vector ISA
 capabilities onto both Power ISA LD/ST with immediate and to
-LD/ST Indexed. They present subtly different Mode tables.
+LD/ST Indexed. They present subtly different Mode tables, which, due
+to lack of space, have the following quirks:
+
+* LD/ST Immediate has no individual control over src/dest zeroing,
+  whereas LD/ST Indexed does.
+* LD/ST Immediate has no Saturated Pack/Unpack (Arithmetic Mode does)
+* LD/ST Indexed has no Pack/Unpack (REMAP may be used instead)
 
 # Format and fields