From: Eddie Hung <eddie@fpgeh.com>
Date: Sat, 28 Sep 2019 00:00:19 +0000 (-0700)
Subject: Fix typo
X-Git-Tag: working-ls180~1027
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=d963e8c2c6207ad98d48dc528922ad58c030173f;p=yosys.git

Fix typo
---

diff --git a/kernel/rtlil.cc b/kernel/rtlil.cc
index 17be28f78..ded1cd60e 100644
--- a/kernel/rtlil.cc
+++ b/kernel/rtlil.cc
@@ -1528,7 +1528,7 @@ std::vector<RTLIL::Wire*> RTLIL::Module::selected_wires() const
 std::vector<RTLIL::Cell*> RTLIL::Module::selected_cells() const
 {
 	std::vector<RTLIL::Cell*> result;
-	result.reserve(wires_.size());
+	result.reserve(cells_.size());
 	for (auto &it : cells_)
 		if (design->selected(this, it.second))
 			result.push_back(it.second);