From: Cesar Strauss <cestrauss@gmail.com>
Date: Thu, 21 May 2020 09:05:57 +0000 (-0300)
Subject: Fixed typo and left-over from refactoring
X-Git-Tag: div_pipeline~1002
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=d9724d6fed90959a78799c6e48667d31abd3a091;p=soc.git

Fixed typo and left-over from refactoring
---

diff --git a/src/soc/experiment/compalu_multi.py b/src/soc/experiment/compalu_multi.py
index adbecd97..0785b753 100644
--- a/src/soc/experiment/compalu_multi.py
+++ b/src/soc/experiment/compalu_multi.py
@@ -83,7 +83,7 @@ class CompUnitRecord(RecordObject):
             j = i + 1 # name numbering to match dest1/2...
             name = "dest%d_i" % j
             dreg = Signal(rwid, name=name, reset_less=True)
-            setattr(self, name, sreg)
+            setattr(self, name, dreg)
             dst.append(dreg)
         self._dest = dst
 
@@ -113,7 +113,6 @@ class MultiCompUnit(Elaboratable):
             name = "src%d_i" % j
             setattr(self, name, getattr(cu, name))
 
-        dst = []
         for i in range(n_dst):
             j = i + 1 # name numbering to match dest1/2...
             name = "dest%d_i" % j