From: lkcl <lkcl@web>
Date: Sun, 7 Aug 2022 11:39:42 +0000 (+0100)
Subject: (no commit message)
X-Git-Tag: opf_rfc_ls005_v1~903
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=d98e6a290691f94d1276e299ba83c98f677f7812;p=libreriscv.git

---

diff --git a/openpower/sv.mdwn b/openpower/sv.mdwn
index d0a95fe59..b7598dd5f 100644
--- a/openpower/sv.mdwn
+++ b/openpower/sv.mdwn
@@ -314,6 +314,8 @@ up-to-date. None of them require or depend on PackedSIMD VSX (or VMX).
 
 Examples experiments future ideas discussion:
 
+* [Scalar register access](https://bugs.libre-soc.org/show_bug.cgi?id=905)
+  above r31 and CR7.
 * [[sv/propagation]] Context propagation including svp64, swizzle and remap
 * [[sv/masked_vector_chaining]]
 * [[sv/discussion]]