From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Wed, 7 Nov 2018 11:49:00 +0000 (+0000)
Subject: mulh* redirect through rv_mul, to save on code
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=d98fac9b36dcfe34ae5721f01e1b1f2eb2c90c16;p=riscv-isa-sim.git

mulh* redirect through rv_mul, to save on code
---

diff --git a/riscv/sv_insn_redirect.cc b/riscv/sv_insn_redirect.cc
index 1dcc3d4..cfdc6dc 100644
--- a/riscv/sv_insn_redirect.cc
+++ b/riscv/sv_insn_redirect.cc
@@ -605,17 +605,17 @@ sv_sreg_t sv_proc_t::rv_mul(sv_sreg_t const & lhs, sv_sreg_t const & rhs)
 /* 32-bit mulh/mulhu/mulhsu */
 sv_reg_t sv_proc_t::rv_mulhu(sv_reg_t const & lhs, sv_reg_t const & rhs)
 {
-    return (lhs * rhs) >> 32;
+    return rv_mul(lhs, rhs) >> 32;
 }
 
 sv_sreg_t sv_proc_t::rv_mulhsu(sv_sreg_t const & lhs, sv_reg_t const & rhs)
 {
-    return (lhs * rhs) >> 32;
+    return rv_mul(lhs, rhs) >> 32;
 }
 
 sv_sreg_t sv_proc_t::rv_mulh(sv_sreg_t const & lhs, sv_sreg_t const & rhs)
 {
-    return (lhs * rhs) >> 32;
+    return rv_mul(lhs, rhs) >> 32;
 }
 
 /* 64-bit mulh/mulhu/mulhsu */