From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Thu, 11 May 2023 20:02:37 +0000 (+0100)
Subject: corrections to dd-ffirst tests when VLi=0, the write to regfile
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=d999008b5fb5fe398b7b01549b4151fafaccbe41;p=openpower-isa.git

corrections to dd-ffirst tests when VLi=0, the write to regfile
is *not* carried out on the failed test. but Rc=1 does (TODO)
---

diff --git a/src/openpower/decoder/isa/test_caller_svp64_dd_ffirst.py b/src/openpower/decoder/isa/test_caller_svp64_dd_ffirst.py
index 40e31b1c..200e7d81 100644
--- a/src/openpower/decoder/isa/test_caller_svp64_dd_ffirst.py
+++ b/src/openpower/decoder/isa/test_caller_svp64_dd_ffirst.py
@@ -47,9 +47,10 @@ class DecoderTestCase(FHDLTestCase):
             expected_vl = 0
             for i in range(4):
                 result = expected[i] - gprs[8]
-                expected[i] = result
                 if result <= 0:
                     break
+                # VLi=0 - test comes FIRST!
+                expected[i] = result
                 # only write out if successful
                 expected_vl += 1
             for i, v in enumerate(res):
@@ -91,9 +92,10 @@ class DecoderTestCase(FHDLTestCase):
             expected = deepcopy(vec)
             for i in range(4):
                 result = expected[i] - gprs[8]
-                expected[i] = result
                 if result == 0:
                     break
+                # VLi=0 - test comes FIRST!
+                expected[i] = result
             for i, v in enumerate(res):
                 self.assertEqual(v, expected[i])
 
@@ -133,9 +135,10 @@ class DecoderTestCase(FHDLTestCase):
             expected = deepcopy(vec)
             for i in range(4):
                 result = expected[i] - gprs[8]
-                expected[i] = result
                 if result == 0:
                     break
+                # VLi=0 - test comes FIRST!
+                expected[i] = result
             for i, v in enumerate(res):
                 self.assertEqual(v, expected[i])
 
@@ -145,6 +148,8 @@ class DecoderTestCase(FHDLTestCase):
             self.assertEqual(sim.svstate.dststep, 0)
 
     def test_sv_addi_ffirst_vli(self):
+        """data-dependent fail-first with VLi=1, the test comes *after* write
+        """
         lst = SVP64Asm(["sv.subf/ff=RC1/vli *0,8,*0"
                         ])
         lst = list(lst)
@@ -174,6 +179,7 @@ class DecoderTestCase(FHDLTestCase):
             # confirm that the results are as expected
             expected = deepcopy(vec)
             for i in range(4):
+                # VLi=1 - test comes AFTER write!
                 expected[i] -= gprs[8]
                 if expected[i] == 0:
                     break