From: Marcelina Koƛcielnicka Date: Tue, 25 May 2021 20:39:50 +0000 (+0200) Subject: mem/extract_rdff: Fix "no FF made" edge case. X-Git-Tag: yosys-0.10~162 X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=d99fce3bc77a42563e1e270172e08ec25d58c7ab;p=yosys.git mem/extract_rdff: Fix "no FF made" edge case. When converting a sync transparent read port with const address to async read port, nothing at all needs to be done other than clk_enable change, and thus we have no FF cell to return. Handle this case correctly in the helper and in its users. --- diff --git a/kernel/mem.cc b/kernel/mem.cc index 5d0a01dd2..fe88be5d7 100644 --- a/kernel/mem.cc +++ b/kernel/mem.cc @@ -579,7 +579,8 @@ Cell *Mem::extract_rdff(int idx, FfInitVals *initvals) { if (port.addr[i].wire) width++; - if (width) { + if (width) + { SigSpec sig_q = module->addWire(stringf("$%s$rdreg[%d]$q", memid.c_str(), idx), width); SigSpec sig_d; @@ -591,6 +592,8 @@ Cell *Mem::extract_rdff(int idx, FfInitVals *initvals) { } c = module->addDff(stringf("$%s$rdreg[%d]", memid.c_str(), idx), port.clk, sig_d, sig_q, port.clk_polarity); + } else { + c = nullptr; } } else diff --git a/passes/memory/memory_nordff.cc b/passes/memory/memory_nordff.cc index 665efceb2..80f78ca77 100644 --- a/passes/memory/memory_nordff.cc +++ b/passes/memory/memory_nordff.cc @@ -57,9 +57,12 @@ struct MemoryNordffPass : public Pass { for (auto &mem : Mem::get_selected_memories(module)) { bool changed = false; - for (int i = 0; i < GetSize(mem.rd_ports); i++) - if (mem.extract_rdff(i, &initvals)) + for (int i = 0; i < GetSize(mem.rd_ports); i++) { + if (mem.rd_ports[i].clk_enable) { + mem.extract_rdff(i, &initvals); changed = true; + } + } if (changed) mem.emit();