From: Ruben Undheim <ruben.undheim@gmail.com>
Date: Sat, 20 Oct 2018 09:57:39 +0000 (+0200)
Subject: Fixed memory leak
X-Git-Tag: yosys-0.9~434^2~2
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=d9a438101298710b9dadd4e7a1cb0041e8ba4199;p=yosys.git

Fixed memory leak
---

diff --git a/frontends/ast/ast.cc b/frontends/ast/ast.cc
index 7600e2912..1f2ecffde 100644
--- a/frontends/ast/ast.cc
+++ b/frontends/ast/ast.cc
@@ -1120,6 +1120,7 @@ void AstModule::reprocess_module(RTLIL::Design *design, dict<RTLIL::IdString, RT
 
 	// Generate RTLIL from AST for the new module and add to the design:
 	AstModule *newmod = process_module(new_ast, false);
+	delete(new_ast);
 	design->add(newmod);
 	RTLIL::Module* mod = design->module(original_name);
 	if (is_top)