From: lkcl <lkcl@web>
Date: Wed, 26 Apr 2023 11:26:44 +0000 (+0100)
Subject: (no commit message)
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=d9ab1bf6ed9d7e5422125809cb72e746916156d1;p=libreriscv.git

---

diff --git a/openpower/sv/rfc/ls007.mdwn b/openpower/sv/rfc/ls007.mdwn
index c19c7b472..9385444c4 100644
--- a/openpower/sv/rfc/ls007.mdwn
+++ b/openpower/sv/rfc/ls007.mdwn
@@ -52,10 +52,8 @@ Instructions added
 **Keywords**:
 
 ```
-GPR, CR-Field, bit-manipulation, ternary, binary, dynamic, look-up-table
-(LUT), FPGA, JIT
+GPR, CR-Field, bit-manipulation, ternary, binary, dynamic, look-up-table (LUT), FPGA, JIT
 ```
-
 **Motivation**
 
 * `ternlogi` is similar to existing `and`/`or`/`xor`/etc. instructions, but