From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Fri, 30 Dec 2022 13:20:56 +0000 (+0000)
Subject: add misaligned mem test
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=d9ad6b728bbc46efd4846d0670e8ae126381bc7a;p=openpower-isa.git

add misaligned mem test
---

diff --git a/src/openpower/decoder/isa/test_mem.py b/src/openpower/decoder/isa/test_mem.py
index 4436d07f..bd847c26 100644
--- a/src/openpower/decoder/isa/test_mem.py
+++ b/src/openpower/decoder/isa/test_mem.py
@@ -9,13 +9,21 @@ from openpower.util import log
 
 class TestMem(unittest.TestCase):
 
-    def test_mem_align_ld(self):
+    def test_mem_align_st(self):
         m = Mem(row_bytes=8, initial_mem={})
         m.st(4, 0x12345678, width=4, swap=False)
         d = m.dump()
         log ("dict", d)
         self.assertEqual(d, [(0, 0x1234567800000000)])
 
+    def test_mem_misalign_st(self):
+        m = Mem(row_bytes=8, initial_mem={})
+        m.st(4, 0x912345678, width=8, swap=False)
+        d = m.dump()
+        log ("dict", d)
+        self.assertEqual(d, [(0, 0x1234567800000000),
+                              8, 0x0000000000000009])
+
 
 if __name__ == '__main__':
     unittest.main()