From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Sat, 16 Feb 2019 08:48:21 +0000 (+0000)
Subject: move value, ack and stb to separate convenience class
X-Git-Tag: ls180-24jan2020~1970
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=d9b1bf93a9a18746f103210ace6fa592cd8c3fde;p=ieee754fpu.git

move value, ack and stb to separate convenience class
---

diff --git a/src/add/nmigen_add_experiment.py b/src/add/nmigen_add_experiment.py
index 2de35570..cad063c1 100644
--- a/src/add/nmigen_add_experiment.py
+++ b/src/add/nmigen_add_experiment.py
@@ -92,22 +92,25 @@ class FPNum:
     def is_denormalised(self):
         return (self.e == self.N126) & (self.m[23] == 0)
 
-
-class FPADD:
+class FPOp:
     def __init__(self, width):
         self.width = width
 
-        self.in_a     = Signal(width)
-        self.in_a_stb = Signal()
-        self.in_a_ack = Signal()
+        self.v     = Signal(width)
+        self.stb = Signal()
+        self.ack = Signal()
+
+    def ports(self):
+        return [self.v, self.stb, self.ack]
+
 
-        self.in_b     = Signal(width)
-        self.in_b_stb = Signal()
-        self.in_b_ack = Signal()
+class FPADD:
+    def __init__(self, width):
+        self.width = width
 
-        self.out_z     = Signal(width)
-        self.out_z_stb = Signal()
-        self.out_z_ack = Signal()
+        self.in_a     = FPOp(width)
+        self.in_b     = FPOp(width)
+        self.out_z     = FPOp(width)
 
     def get_fragment(self, platform=None):
         m = Module()
@@ -129,27 +132,27 @@ class FPADD:
             # gets operand a
 
             with m.State("get_a"):
-                with m.If((self.in_a_ack) & (self.in_a_stb)):
+                with m.If((self.in_a.ack) & (self.in_a.stb)):
                     m.next = "get_b"
                     m.d.sync += [
-                        a.v.eq(self.in_a),
-                        self.in_a_ack.eq(0)
+                        a.v.eq(self.in_a.v),
+                        self.in_a.ack.eq(0)
                     ]
                 with m.Else():
-                    m.d.sync += self.in_a_ack.eq(1)
+                    m.d.sync += self.in_a.ack.eq(1)
 
             # ******
             # gets operand b
 
             with m.State("get_b"):
-                with m.If((self.in_b_ack) & (self.in_b_stb)):
+                with m.If((self.in_b.ack) & (self.in_b.stb)):
                     m.next = "unpack"
                     m.d.sync += [
-                        b.v.eq(self.in_b),
-                        self.in_b_ack.eq(0)
+                        b.v.eq(self.in_b.v),
+                        self.in_b.ack.eq(0)
                     ]
                 with m.Else():
-                    m.d.sync += self.in_b_ack.eq(1)
+                    m.d.sync += self.in_b.ack.eq(1)
 
             # ******
             # unpacks operands into sign, mantissa and exponent
@@ -352,11 +355,11 @@ class FPADD:
 
             with m.State("put_z"):
               m.d.sync += [
-                  self.out_z_stb.eq(1),
-                  self.out_z.eq(z.v)
+                  self.out_z.stb.eq(1),
+                  self.out_z.v.eq(z.v)
               ]
-              with m.If(self.out_z_stb & self.out_z_ack):
-                  m.d.sync += self.out_z_stb.eq(0)
+              with m.If(self.out_z.stb & self.out_z.ack):
+                  m.d.sync += self.out_z.stb.eq(0)
                   m.next = "get_a"
 
         return m
@@ -364,16 +367,11 @@ class FPADD:
 
 if __name__ == "__main__":
     alu = FPADD(width=32)
-    main(alu, ports=[
-                    alu.in_a, alu.in_a_stb, alu.in_a_ack,
-                    alu.in_b, alu.in_b_stb, alu.in_b_ack,
-                    alu.out_z, alu.out_z_stb, alu.out_z_ack,
-        ])
+    main(alu, ports=alu.in_a.ports() + alu.in_b.ports() + alu.out_z.ports())
 
 
     # works... but don't use, just do "python fname.py convert -t v"
     #print (verilog.convert(alu, ports=[
-    #                alu.in_a, alu.in_a_stb, alu.in_a_ack,
-    #                alu.in_b, alu.in_b_stb, alu.in_b_ack,
-    #                alu.out_z, alu.out_z_stb, alu.out_z_ack,
-    #    ]))
+    #                        ports=alu.in_a.ports() + \
+    #                              alu.in_b.ports() + \
+    #                              alu.out_z.ports())
diff --git a/src/add/test_add.py b/src/add/test_add.py
index a7d7c3d3..def8c475 100644
--- a/src/add/test_add.py
+++ b/src/add/test_add.py
@@ -17,32 +17,32 @@ class ORGate:
         return m
 
 def check_case(dut, a, b, z):
-    yield dut.in_a.eq(a)
-    yield dut.in_a_stb.eq(1)
+    yield dut.in_a.v.eq(a)
+    yield dut.in_a.stb.eq(1)
     yield
     yield
-    a_ack = (yield dut.in_a_ack)
+    a_ack = (yield dut.in_a.ack)
     assert a_ack == 0
-    yield dut.in_b.eq(b)
-    yield dut.in_b_stb.eq(1)
-    b_ack = (yield dut.in_b_ack)
+    yield dut.in_b.v.eq(b)
+    yield dut.in_b.stb.eq(1)
+    b_ack = (yield dut.in_b.ack)
     assert b_ack == 0
 
     while True:
         yield
-        out_z_stb = (yield dut.out_z_stb)
+        out_z_stb = (yield dut.out_z.stb)
         if not out_z_stb:
             continue
-        yield dut.in_a_stb.eq(0)
-        yield dut.in_b_stb.eq(0)
-        yield dut.out_z_ack.eq(1)
+        yield dut.in_a.stb.eq(0)
+        yield dut.in_b.stb.eq(0)
+        yield dut.out_z.ack.eq(1)
         yield
-        yield dut.out_z_ack.eq(0)
+        yield dut.out_z.ack.eq(0)
         yield
         yield
         break
 
-    out_z = yield dut.out_z
+    out_z = yield dut.out_z.v
     assert out_z == z, "Output z 0x%x not equal to expected 0x%x" % (out_z, z)
 
 def testbench(dut):