From: Jim Wilson <jimw@sifive.com>
Date: Thu, 28 Dec 2017 21:21:46 +0000 (-0800)
Subject: RISC-V: Add missing privileged spec registers.
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=d9be0c189a9a9b77a6bf4501f8891544b8ce9593;p=binutils-gdb.git

RISC-V: Add missing privileged spec registers.

	gas/
	* testsuite/gas/riscv/priv-reg.d, testsuite/gas/riscv/priv-reg.s: New.

	include/
	* opcode/riscv-opc.h (DECLARE_CSR): Add missing privileged registers.
	Sort to match privileged spec documentation order.
	(DECLARE_CSR_ALIAS): Add ubadaddr, and comments.
---

diff --git a/gas/ChangeLog b/gas/ChangeLog
index 3d12e935821..eeeff519020 100644
--- a/gas/ChangeLog
+++ b/gas/ChangeLog
@@ -1,3 +1,7 @@
+2017-12-28  Jim Wilson  <jimw@sifive.com>
+
+	* testsuite/gas/riscv/priv-reg.d, testsuite/gas/riscv/priv-reg.s: New.
+
 2017-12-20  Jim Wilson  <jimw@sifive.com>
 
 	* config/tc-riscv.c (risc_ip) <o>: Add comment.
diff --git a/gas/testsuite/gas/riscv/priv-reg.d b/gas/testsuite/gas/riscv/priv-reg.d
new file mode 100644
index 00000000000..2a650df248d
--- /dev/null
+++ b/gas/testsuite/gas/riscv/priv-reg.d
@@ -0,0 +1,251 @@
+#as: -march=rv32i
+#objdump: -dr
+
+.*:[ 	]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <.text>:
+[ 	]+0:[ 	]+00002573[ 	]+csrr[ 	]+a0,ustatus
+[ 	]+4:[ 	]+00402573[ 	]+csrr[ 	]+a0,uie
+[ 	]+8:[ 	]+00502573[ 	]+csrr[ 	]+a0,utvec
+[ 	]+c:[ 	]+04002573[ 	]+csrr[ 	]+a0,uscratch
+[ 	]+10:[ 	]+04102573[ 	]+csrr[ 	]+a0,uepc
+[ 	]+14:[ 	]+04202573[ 	]+csrr[ 	]+a0,ucause
+[ 	]+18:[ 	]+04302573[ 	]+csrr[ 	]+a0,utval
+[ 	]+1c:[ 	]+04402573[ 	]+csrr[ 	]+a0,uip
+[ 	]+20:[ 	]+00102573[ 	]+frflags[ 	]+a0
+[ 	]+24:[ 	]+00202573[ 	]+frrm[ 	]+a0
+[ 	]+28:[ 	]+00302573[ 	]+frsr[ 	]+a0
+[ 	]+2c:[ 	]+c0002573[ 	]+rdcycle[ 	]+a0
+[ 	]+30:[ 	]+c0102573[ 	]+rdtime[ 	]+a0
+[ 	]+34:[ 	]+c0202573[ 	]+rdinstret[ 	]+a0
+[ 	]+38:[ 	]+c0302573[ 	]+csrr[ 	]+a0,hpmcounter3
+[ 	]+3c:[ 	]+c0402573[ 	]+csrr[ 	]+a0,hpmcounter4
+[ 	]+40:[ 	]+c0502573[ 	]+csrr[ 	]+a0,hpmcounter5
+[ 	]+44:[ 	]+c0602573[ 	]+csrr[ 	]+a0,hpmcounter6
+[ 	]+48:[ 	]+c0702573[ 	]+csrr[ 	]+a0,hpmcounter7
+[ 	]+4c:[ 	]+c0802573[ 	]+csrr[ 	]+a0,hpmcounter8
+[ 	]+50:[ 	]+c0902573[ 	]+csrr[ 	]+a0,hpmcounter9
+[ 	]+54:[ 	]+c0a02573[ 	]+csrr[ 	]+a0,hpmcounter10
+[ 	]+58:[ 	]+c0b02573[ 	]+csrr[ 	]+a0,hpmcounter11
+[ 	]+5c:[ 	]+c0c02573[ 	]+csrr[ 	]+a0,hpmcounter12
+[ 	]+60:[ 	]+c0d02573[ 	]+csrr[ 	]+a0,hpmcounter13
+[ 	]+64:[ 	]+c0e02573[ 	]+csrr[ 	]+a0,hpmcounter14
+[ 	]+68:[ 	]+c0f02573[ 	]+csrr[ 	]+a0,hpmcounter15
+[ 	]+6c:[ 	]+c1002573[ 	]+csrr[ 	]+a0,hpmcounter16
+[ 	]+70:[ 	]+c1102573[ 	]+csrr[ 	]+a0,hpmcounter17
+[ 	]+74:[ 	]+c1202573[ 	]+csrr[ 	]+a0,hpmcounter18
+[ 	]+78:[ 	]+c1302573[ 	]+csrr[ 	]+a0,hpmcounter19
+[ 	]+7c:[ 	]+c1402573[ 	]+csrr[ 	]+a0,hpmcounter20
+[ 	]+80:[ 	]+c1502573[ 	]+csrr[ 	]+a0,hpmcounter21
+[ 	]+84:[ 	]+c1602573[ 	]+csrr[ 	]+a0,hpmcounter22
+[ 	]+88:[ 	]+c1702573[ 	]+csrr[ 	]+a0,hpmcounter23
+[ 	]+8c:[ 	]+c1802573[ 	]+csrr[ 	]+a0,hpmcounter24
+[ 	]+90:[ 	]+c1902573[ 	]+csrr[ 	]+a0,hpmcounter25
+[ 	]+94:[ 	]+c1a02573[ 	]+csrr[ 	]+a0,hpmcounter26
+[ 	]+98:[ 	]+c1b02573[ 	]+csrr[ 	]+a0,hpmcounter27
+[ 	]+9c:[ 	]+c1c02573[ 	]+csrr[ 	]+a0,hpmcounter28
+[ 	]+a0:[ 	]+c1d02573[ 	]+csrr[ 	]+a0,hpmcounter29
+[ 	]+a4:[ 	]+c1e02573[ 	]+csrr[ 	]+a0,hpmcounter30
+[ 	]+a8:[ 	]+c1f02573[ 	]+csrr[ 	]+a0,hpmcounter31
+[ 	]+ac:[ 	]+c8002573[ 	]+rdcycleh[ 	]+a0
+[ 	]+b0:[ 	]+c8102573[ 	]+rdtimeh[ 	]+a0
+[ 	]+b4:[ 	]+c8202573[ 	]+rdinstreth[ 	]+a0
+[ 	]+b8:[ 	]+c8302573[ 	]+csrr[ 	]+a0,hpmcounter3h
+[ 	]+bc:[ 	]+c8402573[ 	]+csrr[ 	]+a0,hpmcounter4h
+[ 	]+c0:[ 	]+c8502573[ 	]+csrr[ 	]+a0,hpmcounter5h
+[ 	]+c4:[ 	]+c8602573[ 	]+csrr[ 	]+a0,hpmcounter6h
+[ 	]+c8:[ 	]+c8702573[ 	]+csrr[ 	]+a0,hpmcounter7h
+[ 	]+cc:[ 	]+c8802573[ 	]+csrr[ 	]+a0,hpmcounter8h
+[ 	]+d0:[ 	]+c8902573[ 	]+csrr[ 	]+a0,hpmcounter9h
+[ 	]+d4:[ 	]+c8a02573[ 	]+csrr[ 	]+a0,hpmcounter10h
+[ 	]+d8:[ 	]+c8b02573[ 	]+csrr[ 	]+a0,hpmcounter11h
+[ 	]+dc:[ 	]+c8c02573[ 	]+csrr[ 	]+a0,hpmcounter12h
+[ 	]+e0:[ 	]+c8d02573[ 	]+csrr[ 	]+a0,hpmcounter13h
+[ 	]+e4:[ 	]+c8e02573[ 	]+csrr[ 	]+a0,hpmcounter14h
+[ 	]+e8:[ 	]+c8f02573[ 	]+csrr[ 	]+a0,hpmcounter15h
+[ 	]+ec:[ 	]+c9002573[ 	]+csrr[ 	]+a0,hpmcounter16h
+[ 	]+f0:[ 	]+c9102573[ 	]+csrr[ 	]+a0,hpmcounter17h
+[ 	]+f4:[ 	]+c9202573[ 	]+csrr[ 	]+a0,hpmcounter18h
+[ 	]+f8:[ 	]+c9302573[ 	]+csrr[ 	]+a0,hpmcounter19h
+[ 	]+fc:[ 	]+c9402573[ 	]+csrr[ 	]+a0,hpmcounter20h
+[ 	]+100:[ 	]+c9502573[ 	]+csrr[ 	]+a0,hpmcounter21h
+[ 	]+104:[ 	]+c9602573[ 	]+csrr[ 	]+a0,hpmcounter22h
+[ 	]+108:[ 	]+c9702573[ 	]+csrr[ 	]+a0,hpmcounter23h
+[ 	]+10c:[ 	]+c9802573[ 	]+csrr[ 	]+a0,hpmcounter24h
+[ 	]+110:[ 	]+c9902573[ 	]+csrr[ 	]+a0,hpmcounter25h
+[ 	]+114:[ 	]+c9a02573[ 	]+csrr[ 	]+a0,hpmcounter26h
+[ 	]+118:[ 	]+c9b02573[ 	]+csrr[ 	]+a0,hpmcounter27h
+[ 	]+11c:[ 	]+c9c02573[ 	]+csrr[ 	]+a0,hpmcounter28h
+[ 	]+120:[ 	]+c9d02573[ 	]+csrr[ 	]+a0,hpmcounter29h
+[ 	]+124:[ 	]+c9e02573[ 	]+csrr[ 	]+a0,hpmcounter30h
+[ 	]+128:[ 	]+c9f02573[ 	]+csrr[ 	]+a0,hpmcounter31h
+[ 	]+12c:[ 	]+10002573[ 	]+csrr[ 	]+a0,sstatus
+[ 	]+130:[ 	]+10202573[ 	]+csrr[ 	]+a0,sedeleg
+[ 	]+134:[ 	]+10302573[ 	]+csrr[ 	]+a0,sideleg
+[ 	]+138:[ 	]+10402573[ 	]+csrr[ 	]+a0,sie
+[ 	]+13c:[ 	]+10502573[ 	]+csrr[ 	]+a0,stvec
+[ 	]+140:[ 	]+14002573[ 	]+csrr[ 	]+a0,sscratch
+[ 	]+144:[ 	]+14102573[ 	]+csrr[ 	]+a0,sepc
+[ 	]+148:[ 	]+14202573[ 	]+csrr[ 	]+a0,scause
+[ 	]+14c:[ 	]+14302573[ 	]+csrr[ 	]+a0,sbadaddr
+[ 	]+150:[ 	]+14402573[ 	]+csrr[ 	]+a0,sip
+[ 	]+154:[ 	]+18002573[ 	]+csrr[ 	]+a0,satp
+[ 	]+158:[ 	]+20002573[ 	]+csrr[ 	]+a0,hstatus
+[ 	]+15c:[ 	]+20202573[ 	]+csrr[ 	]+a0,hedeleg
+[ 	]+160:[ 	]+20302573[ 	]+csrr[ 	]+a0,hideleg
+[ 	]+164:[ 	]+20402573[ 	]+csrr[ 	]+a0,hie
+[ 	]+168:[ 	]+20502573[ 	]+csrr[ 	]+a0,htvec
+[ 	]+16c:[ 	]+24002573[ 	]+csrr[ 	]+a0,hscratch
+[ 	]+170:[ 	]+24102573[ 	]+csrr[ 	]+a0,hepc
+[ 	]+174:[ 	]+24202573[ 	]+csrr[ 	]+a0,hcause
+[ 	]+178:[ 	]+24302573[ 	]+csrr[ 	]+a0,hbadaddr
+[ 	]+17c:[ 	]+24402573[ 	]+csrr[ 	]+a0,hip
+[ 	]+180:[ 	]+f1102573[ 	]+csrr[ 	]+a0,mvendorid
+[ 	]+184:[ 	]+f1202573[ 	]+csrr[ 	]+a0,marchid
+[ 	]+188:[ 	]+f1302573[ 	]+csrr[ 	]+a0,mimpid
+[ 	]+18c:[ 	]+f1402573[ 	]+csrr[ 	]+a0,mhartid
+[ 	]+190:[ 	]+30002573[ 	]+csrr[ 	]+a0,mstatus
+[ 	]+194:[ 	]+30102573[ 	]+csrr[ 	]+a0,misa
+[ 	]+198:[ 	]+30202573[ 	]+csrr[ 	]+a0,medeleg
+[ 	]+19c:[ 	]+30302573[ 	]+csrr[ 	]+a0,mideleg
+[ 	]+1a0:[ 	]+30402573[ 	]+csrr[ 	]+a0,mie
+[ 	]+1a4:[ 	]+30502573[ 	]+csrr[ 	]+a0,mtvec
+[ 	]+1a8:[ 	]+34002573[ 	]+csrr[ 	]+a0,mscratch
+[ 	]+1ac:[ 	]+34102573[ 	]+csrr[ 	]+a0,mepc
+[ 	]+1b0:[ 	]+34202573[ 	]+csrr[ 	]+a0,mcause
+[ 	]+1b4:[ 	]+34302573[ 	]+csrr[ 	]+a0,mbadaddr
+[ 	]+1b8:[ 	]+34402573[ 	]+csrr[ 	]+a0,mip
+[ 	]+1bc:[ 	]+38002573[ 	]+csrr[ 	]+a0,mbase
+[ 	]+1c0:[ 	]+38102573[ 	]+csrr[ 	]+a0,mbound
+[ 	]+1c4:[ 	]+38202573[ 	]+csrr[ 	]+a0,mibase
+[ 	]+1c8:[ 	]+38302573[ 	]+csrr[ 	]+a0,mibound
+[ 	]+1cc:[ 	]+38402573[ 	]+csrr[ 	]+a0,mdbase
+[ 	]+1d0:[ 	]+38502573[ 	]+csrr[ 	]+a0,mdbound
+[ 	]+1d4:[ 	]+b0002573[ 	]+csrr[ 	]+a0,mcycle
+[ 	]+1d8:[ 	]+b0202573[ 	]+csrr[ 	]+a0,minstret
+[ 	]+1dc:[ 	]+b0302573[ 	]+csrr[ 	]+a0,mhpmcounter3
+[ 	]+1e0:[ 	]+b0402573[ 	]+csrr[ 	]+a0,mhpmcounter4
+[ 	]+1e4:[ 	]+b0502573[ 	]+csrr[ 	]+a0,mhpmcounter5
+[ 	]+1e8:[ 	]+b0602573[ 	]+csrr[ 	]+a0,mhpmcounter6
+[ 	]+1ec:[ 	]+b0702573[ 	]+csrr[ 	]+a0,mhpmcounter7
+[ 	]+1f0:[ 	]+b0802573[ 	]+csrr[ 	]+a0,mhpmcounter8
+[ 	]+1f4:[ 	]+b0902573[ 	]+csrr[ 	]+a0,mhpmcounter9
+[ 	]+1f8:[ 	]+b0a02573[ 	]+csrr[ 	]+a0,mhpmcounter10
+[ 	]+1fc:[ 	]+b0b02573[ 	]+csrr[ 	]+a0,mhpmcounter11
+[ 	]+200:[ 	]+b0c02573[ 	]+csrr[ 	]+a0,mhpmcounter12
+[ 	]+204:[ 	]+b0d02573[ 	]+csrr[ 	]+a0,mhpmcounter13
+[ 	]+208:[ 	]+b0e02573[ 	]+csrr[ 	]+a0,mhpmcounter14
+[ 	]+20c:[ 	]+b0f02573[ 	]+csrr[ 	]+a0,mhpmcounter15
+[ 	]+210:[ 	]+b1002573[ 	]+csrr[ 	]+a0,mhpmcounter16
+[ 	]+214:[ 	]+b1102573[ 	]+csrr[ 	]+a0,mhpmcounter17
+[ 	]+218:[ 	]+b1202573[ 	]+csrr[ 	]+a0,mhpmcounter18
+[ 	]+21c:[ 	]+b1302573[ 	]+csrr[ 	]+a0,mhpmcounter19
+[ 	]+220:[ 	]+b1402573[ 	]+csrr[ 	]+a0,mhpmcounter20
+[ 	]+224:[ 	]+b1502573[ 	]+csrr[ 	]+a0,mhpmcounter21
+[ 	]+228:[ 	]+b1602573[ 	]+csrr[ 	]+a0,mhpmcounter22
+[ 	]+22c:[ 	]+b1702573[ 	]+csrr[ 	]+a0,mhpmcounter23
+[ 	]+230:[ 	]+b1802573[ 	]+csrr[ 	]+a0,mhpmcounter24
+[ 	]+234:[ 	]+b1902573[ 	]+csrr[ 	]+a0,mhpmcounter25
+[ 	]+238:[ 	]+b1a02573[ 	]+csrr[ 	]+a0,mhpmcounter26
+[ 	]+23c:[ 	]+b1b02573[ 	]+csrr[ 	]+a0,mhpmcounter27
+[ 	]+240:[ 	]+b1c02573[ 	]+csrr[ 	]+a0,mhpmcounter28
+[ 	]+244:[ 	]+b1d02573[ 	]+csrr[ 	]+a0,mhpmcounter29
+[ 	]+248:[ 	]+b1e02573[ 	]+csrr[ 	]+a0,mhpmcounter30
+[ 	]+24c:[ 	]+b1f02573[ 	]+csrr[ 	]+a0,mhpmcounter31
+[ 	]+250:[ 	]+b8002573[ 	]+csrr[ 	]+a0,mcycleh
+[ 	]+254:[ 	]+b8202573[ 	]+csrr[ 	]+a0,minstreth
+[ 	]+258:[ 	]+b8302573[ 	]+csrr[ 	]+a0,mhpmcounter3h
+[ 	]+25c:[ 	]+b8402573[ 	]+csrr[ 	]+a0,mhpmcounter4h
+[ 	]+260:[ 	]+b8502573[ 	]+csrr[ 	]+a0,mhpmcounter5h
+[ 	]+264:[ 	]+b8602573[ 	]+csrr[ 	]+a0,mhpmcounter6h
+[ 	]+268:[ 	]+b8702573[ 	]+csrr[ 	]+a0,mhpmcounter7h
+[ 	]+26c:[ 	]+b8802573[ 	]+csrr[ 	]+a0,mhpmcounter8h
+[ 	]+270:[ 	]+b8902573[ 	]+csrr[ 	]+a0,mhpmcounter9h
+[ 	]+274:[ 	]+b8a02573[ 	]+csrr[ 	]+a0,mhpmcounter10h
+[ 	]+278:[ 	]+b8b02573[ 	]+csrr[ 	]+a0,mhpmcounter11h
+[ 	]+27c:[ 	]+b8c02573[ 	]+csrr[ 	]+a0,mhpmcounter12h
+[ 	]+280:[ 	]+b8d02573[ 	]+csrr[ 	]+a0,mhpmcounter13h
+[ 	]+284:[ 	]+b8e02573[ 	]+csrr[ 	]+a0,mhpmcounter14h
+[ 	]+288:[ 	]+b8f02573[ 	]+csrr[ 	]+a0,mhpmcounter15h
+[ 	]+28c:[ 	]+b9002573[ 	]+csrr[ 	]+a0,mhpmcounter16h
+[ 	]+290:[ 	]+b9102573[ 	]+csrr[ 	]+a0,mhpmcounter17h
+[ 	]+294:[ 	]+b9202573[ 	]+csrr[ 	]+a0,mhpmcounter18h
+[ 	]+298:[ 	]+b9302573[ 	]+csrr[ 	]+a0,mhpmcounter19h
+[ 	]+29c:[ 	]+b9402573[ 	]+csrr[ 	]+a0,mhpmcounter20h
+[ 	]+2a0:[ 	]+b9502573[ 	]+csrr[ 	]+a0,mhpmcounter21h
+[ 	]+2a4:[ 	]+b9602573[ 	]+csrr[ 	]+a0,mhpmcounter22h
+[ 	]+2a8:[ 	]+b9702573[ 	]+csrr[ 	]+a0,mhpmcounter23h
+[ 	]+2ac:[ 	]+b9802573[ 	]+csrr[ 	]+a0,mhpmcounter24h
+[ 	]+2b0:[ 	]+b9902573[ 	]+csrr[ 	]+a0,mhpmcounter25h
+[ 	]+2b4:[ 	]+b9a02573[ 	]+csrr[ 	]+a0,mhpmcounter26h
+[ 	]+2b8:[ 	]+b9b02573[ 	]+csrr[ 	]+a0,mhpmcounter27h
+[ 	]+2bc:[ 	]+b9c02573[ 	]+csrr[ 	]+a0,mhpmcounter28h
+[ 	]+2c0:[ 	]+b9d02573[ 	]+csrr[ 	]+a0,mhpmcounter29h
+[ 	]+2c4:[ 	]+b9e02573[ 	]+csrr[ 	]+a0,mhpmcounter30h
+[ 	]+2c8:[ 	]+b9f02573[ 	]+csrr[ 	]+a0,mhpmcounter31h
+[ 	]+2cc:[ 	]+32002573[ 	]+csrr[ 	]+a0,mucounteren
+[ 	]+2d0:[ 	]+32102573[ 	]+csrr[ 	]+a0,mscounteren
+[ 	]+2d4:[ 	]+32202573[ 	]+csrr[ 	]+a0,mhcounteren
+[ 	]+2d8:[ 	]+32302573[ 	]+csrr[ 	]+a0,mhpmevent3
+[ 	]+2dc:[ 	]+32402573[ 	]+csrr[ 	]+a0,mhpmevent4
+[ 	]+2e0:[ 	]+32502573[ 	]+csrr[ 	]+a0,mhpmevent5
+[ 	]+2e4:[ 	]+32602573[ 	]+csrr[ 	]+a0,mhpmevent6
+[ 	]+2e8:[ 	]+32702573[ 	]+csrr[ 	]+a0,mhpmevent7
+[ 	]+2ec:[ 	]+32802573[ 	]+csrr[ 	]+a0,mhpmevent8
+[ 	]+2f0:[ 	]+32902573[ 	]+csrr[ 	]+a0,mhpmevent9
+[ 	]+2f4:[ 	]+32a02573[ 	]+csrr[ 	]+a0,mhpmevent10
+[ 	]+2f8:[ 	]+32b02573[ 	]+csrr[ 	]+a0,mhpmevent11
+[ 	]+2fc:[ 	]+32c02573[ 	]+csrr[ 	]+a0,mhpmevent12
+[ 	]+300:[ 	]+32d02573[ 	]+csrr[ 	]+a0,mhpmevent13
+[ 	]+304:[ 	]+32e02573[ 	]+csrr[ 	]+a0,mhpmevent14
+[ 	]+308:[ 	]+32f02573[ 	]+csrr[ 	]+a0,mhpmevent15
+[ 	]+30c:[ 	]+33002573[ 	]+csrr[ 	]+a0,mhpmevent16
+[ 	]+310:[ 	]+33102573[ 	]+csrr[ 	]+a0,mhpmevent17
+[ 	]+314:[ 	]+33202573[ 	]+csrr[ 	]+a0,mhpmevent18
+[ 	]+318:[ 	]+33302573[ 	]+csrr[ 	]+a0,mhpmevent19
+[ 	]+31c:[ 	]+33402573[ 	]+csrr[ 	]+a0,mhpmevent20
+[ 	]+320:[ 	]+33502573[ 	]+csrr[ 	]+a0,mhpmevent21
+[ 	]+324:[ 	]+33602573[ 	]+csrr[ 	]+a0,mhpmevent22
+[ 	]+328:[ 	]+33702573[ 	]+csrr[ 	]+a0,mhpmevent23
+[ 	]+32c:[ 	]+33802573[ 	]+csrr[ 	]+a0,mhpmevent24
+[ 	]+330:[ 	]+33902573[ 	]+csrr[ 	]+a0,mhpmevent25
+[ 	]+334:[ 	]+33a02573[ 	]+csrr[ 	]+a0,mhpmevent26
+[ 	]+338:[ 	]+33b02573[ 	]+csrr[ 	]+a0,mhpmevent27
+[ 	]+33c:[ 	]+33c02573[ 	]+csrr[ 	]+a0,mhpmevent28
+[ 	]+340:[ 	]+33d02573[ 	]+csrr[ 	]+a0,mhpmevent29
+[ 	]+344:[ 	]+33e02573[ 	]+csrr[ 	]+a0,mhpmevent30
+[ 	]+348:[ 	]+33f02573[ 	]+csrr[ 	]+a0,mhpmevent31
+[ 	]+34c:[ 	]+7a002573[ 	]+csrr[ 	]+a0,tselect
+[ 	]+350:[ 	]+7a102573[ 	]+csrr[ 	]+a0,tdata1
+[ 	]+354:[ 	]+7a202573[ 	]+csrr[ 	]+a0,tdata2
+[ 	]+358:[ 	]+7a302573[ 	]+csrr[ 	]+a0,tdata3
+[ 	]+35c:[ 	]+7b002573[ 	]+csrr[ 	]+a0,dcsr
+[ 	]+360:[ 	]+7b102573[ 	]+csrr[ 	]+a0,dpc
+[ 	]+364:[ 	]+7b202573[ 	]+csrr[ 	]+a0,dscratch
+[ 	]+368:[ 	]+04302573[ 	]+csrr[ 	]+a0,utval
+[ 	]+36c:[ 	]+10602573[ 	]+csrr[ 	]+a0,scounteren
+[ 	]+370:[ 	]+18002573[ 	]+csrr[ 	]+a0,satp
+[ 	]+374:[ 	]+30602573[ 	]+csrr[ 	]+a0,mcounteren
+[ 	]+378:[ 	]+3a002573[ 	]+csrr[ 	]+a0,pmpcfg0
+[ 	]+37c:[ 	]+3a102573[ 	]+csrr[ 	]+a0,pmpcfg1
+[ 	]+380:[ 	]+3a202573[ 	]+csrr[ 	]+a0,pmpcfg2
+[ 	]+384:[ 	]+3a302573[ 	]+csrr[ 	]+a0,pmpcfg3
+[ 	]+388:[ 	]+3b002573[ 	]+csrr[ 	]+a0,pmpaddr0
+[ 	]+38c:[ 	]+3b102573[ 	]+csrr[ 	]+a0,pmpaddr1
+[ 	]+390:[ 	]+3b202573[ 	]+csrr[ 	]+a0,pmpaddr2
+[ 	]+394:[ 	]+3b302573[ 	]+csrr[ 	]+a0,pmpaddr3
+[ 	]+398:[ 	]+3b402573[ 	]+csrr[ 	]+a0,pmpaddr4
+[ 	]+39c:[ 	]+3b502573[ 	]+csrr[ 	]+a0,pmpaddr5
+[ 	]+3a0:[ 	]+3b602573[ 	]+csrr[ 	]+a0,pmpaddr6
+[ 	]+3a4:[ 	]+3b702573[ 	]+csrr[ 	]+a0,pmpaddr7
+[ 	]+3a8:[ 	]+3b802573[ 	]+csrr[ 	]+a0,pmpaddr8
+[ 	]+3ac:[ 	]+3b902573[ 	]+csrr[ 	]+a0,pmpaddr9
+[ 	]+3b0:[ 	]+3ba02573[ 	]+csrr[ 	]+a0,pmpaddr10
+[ 	]+3b4:[ 	]+3bb02573[ 	]+csrr[ 	]+a0,pmpaddr11
+[ 	]+3b8:[ 	]+3bc02573[ 	]+csrr[ 	]+a0,pmpaddr12
+[ 	]+3bc:[ 	]+3bd02573[ 	]+csrr[ 	]+a0,pmpaddr13
+[ 	]+3c0:[ 	]+3be02573[ 	]+csrr[ 	]+a0,pmpaddr14
+[ 	]+3c4:[ 	]+3bf02573[ 	]+csrr[ 	]+a0,pmpaddr15
diff --git a/gas/testsuite/gas/riscv/priv-reg.s b/gas/testsuite/gas/riscv/priv-reg.s
new file mode 100644
index 00000000000..4774f3651b0
--- /dev/null
+++ b/gas/testsuite/gas/riscv/priv-reg.s
@@ -0,0 +1,267 @@
+	.macro csr val
+	csrr a0,\val
+	.endm
+# 1.9.1 registers
+	csr ustatus
+	csr uie
+	csr utvec
+
+	csr uscratch
+	csr uepc
+	csr ucause
+	csr ubadaddr
+	csr uip
+
+	csr fflags
+	csr frm
+	csr fcsr
+
+	csr cycle
+	csr time
+	csr instret
+	csr hpmcounter3
+	csr hpmcounter4
+	csr hpmcounter5
+	csr hpmcounter6
+	csr hpmcounter7
+	csr hpmcounter8
+	csr hpmcounter9
+	csr hpmcounter10
+	csr hpmcounter11
+	csr hpmcounter12
+	csr hpmcounter13
+	csr hpmcounter14
+	csr hpmcounter15
+	csr hpmcounter16
+	csr hpmcounter17
+	csr hpmcounter18
+	csr hpmcounter19
+	csr hpmcounter20
+	csr hpmcounter21
+	csr hpmcounter22
+	csr hpmcounter23
+	csr hpmcounter24
+	csr hpmcounter25
+	csr hpmcounter26
+	csr hpmcounter27
+	csr hpmcounter28
+	csr hpmcounter29
+	csr hpmcounter30
+	csr hpmcounter31
+	csr cycleh
+	csr timeh
+	csr instreth
+	csr hpmcounter3h
+	csr hpmcounter4h
+	csr hpmcounter5h
+	csr hpmcounter6h
+	csr hpmcounter7h
+	csr hpmcounter8h
+	csr hpmcounter9h
+	csr hpmcounter10h
+	csr hpmcounter11h
+	csr hpmcounter12h
+	csr hpmcounter13h
+	csr hpmcounter14h
+	csr hpmcounter15h
+	csr hpmcounter16h
+	csr hpmcounter17h
+	csr hpmcounter18h
+	csr hpmcounter19h
+	csr hpmcounter20h
+	csr hpmcounter21h
+	csr hpmcounter22h
+	csr hpmcounter23h
+	csr hpmcounter24h
+	csr hpmcounter25h
+	csr hpmcounter26h
+	csr hpmcounter27h
+	csr hpmcounter28h
+	csr hpmcounter29h
+	csr hpmcounter30h
+	csr hpmcounter31h
+
+	csr sstatus
+	csr sedeleg
+	csr sideleg
+	csr sie
+	csr stvec
+
+	csr sscratch
+	csr sepc
+	csr scause
+	csr sbadaddr
+	csr sip
+
+	csr sptbr
+
+	csr hstatus
+	csr hedeleg
+	csr hideleg
+	csr hie
+	csr htvec
+
+	csr hscratch
+	csr hepc
+	csr hcause
+	csr hbadaddr
+	csr hip
+
+	csr mvendorid
+	csr marchid
+	csr mimpid
+	csr mhartid
+
+	csr mstatus
+	csr misa
+	csr medeleg
+	csr mideleg
+	csr mie
+	csr mtvec
+
+	csr mscratch
+	csr mepc
+	csr mcause
+	csr mbadaddr
+	csr mip
+
+	csr mbase
+	csr mbound
+	csr mibase
+	csr mibound
+	csr mdbase
+	csr mdbound
+
+	csr mcycle
+	csr minstret
+	csr mhpmcounter3
+	csr mhpmcounter4
+	csr mhpmcounter5
+	csr mhpmcounter6
+	csr mhpmcounter7
+	csr mhpmcounter8
+	csr mhpmcounter9
+	csr mhpmcounter10
+	csr mhpmcounter11
+	csr mhpmcounter12
+	csr mhpmcounter13
+	csr mhpmcounter14
+	csr mhpmcounter15
+	csr mhpmcounter16
+	csr mhpmcounter17
+	csr mhpmcounter18
+	csr mhpmcounter19
+	csr mhpmcounter20
+	csr mhpmcounter21
+	csr mhpmcounter22
+	csr mhpmcounter23
+	csr mhpmcounter24
+	csr mhpmcounter25
+	csr mhpmcounter26
+	csr mhpmcounter27
+	csr mhpmcounter28
+	csr mhpmcounter29
+	csr mhpmcounter30
+	csr mhpmcounter31
+	csr mcycleh
+	csr minstreth
+	csr mhpmcounter3h
+	csr mhpmcounter4h
+	csr mhpmcounter5h
+	csr mhpmcounter6h
+	csr mhpmcounter7h
+	csr mhpmcounter8h
+	csr mhpmcounter9h
+	csr mhpmcounter10h
+	csr mhpmcounter11h
+	csr mhpmcounter12h
+	csr mhpmcounter13h
+	csr mhpmcounter14h
+	csr mhpmcounter15h
+	csr mhpmcounter16h
+	csr mhpmcounter17h
+	csr mhpmcounter18h
+	csr mhpmcounter19h
+	csr mhpmcounter20h
+	csr mhpmcounter21h
+	csr mhpmcounter22h
+	csr mhpmcounter23h
+	csr mhpmcounter24h
+	csr mhpmcounter25h
+	csr mhpmcounter26h
+	csr mhpmcounter27h
+	csr mhpmcounter28h
+	csr mhpmcounter29h
+	csr mhpmcounter30h
+	csr mhpmcounter31h
+
+	csr mucounteren
+	csr mscounteren
+	csr mhcounteren
+
+	csr mhpmevent3
+	csr mhpmevent4
+	csr mhpmevent5
+	csr mhpmevent6
+	csr mhpmevent7
+	csr mhpmevent8
+	csr mhpmevent9
+	csr mhpmevent10
+	csr mhpmevent11
+	csr mhpmevent12
+	csr mhpmevent13
+	csr mhpmevent14
+	csr mhpmevent15
+	csr mhpmevent16
+	csr mhpmevent17
+	csr mhpmevent18
+	csr mhpmevent19
+	csr mhpmevent20
+	csr mhpmevent21
+	csr mhpmevent22
+	csr mhpmevent23
+	csr mhpmevent24
+	csr mhpmevent25
+	csr mhpmevent26
+	csr mhpmevent27
+	csr mhpmevent28
+	csr mhpmevent29
+	csr mhpmevent30
+	csr mhpmevent31
+
+	csr tselect
+	csr tdata1
+	csr tdata2
+	csr tdata3
+
+	csr dcsr
+	csr dpc
+	csr dscratch
+# 1.10 registers
+	csr utval
+
+	csr scounteren
+	csr satp
+
+	csr mcounteren
+
+	csr pmpcfg0
+	csr pmpcfg1
+	csr pmpcfg2
+	csr pmpcfg3
+	csr pmpaddr0
+	csr pmpaddr1
+	csr pmpaddr2
+	csr pmpaddr3
+	csr pmpaddr4
+	csr pmpaddr5
+	csr pmpaddr6
+	csr pmpaddr7
+	csr pmpaddr8
+	csr pmpaddr9
+	csr pmpaddr10
+	csr pmpaddr11
+	csr pmpaddr12
+	csr pmpaddr13
+	csr pmpaddr14
+	csr pmpaddr15
diff --git a/include/ChangeLog b/include/ChangeLog
index 144c1382ce7..78b3a6b6d41 100644
--- a/include/ChangeLog
+++ b/include/ChangeLog
@@ -1,3 +1,9 @@
+2017-12-28  Jim Wilson  <jimw@sifive.com>
+
+	* opcode/riscv-opc.h (DECLARE_CSR): Add missing privileged registers.
+	Sort to match privileged spec documentation order.
+	(DECLARE_CSR_ALIAS): Add ubadaddr, and comments.
+
 2017-12-19  Tamar Christina  <tamar.christina@arm.com>
 
 	PR gas/22559
diff --git a/include/opcode/riscv-opc.h b/include/opcode/riscv-opc.h
index ee37d3ff505..64635e11342 100644
--- a/include/opcode/riscv-opc.h
+++ b/include/opcode/riscv-opc.h
@@ -567,6 +567,14 @@
 #define MASK_CUSTOM3_RD_RS1  0x707f
 #define MATCH_CUSTOM3_RD_RS1_RS2 0x707b
 #define MASK_CUSTOM3_RD_RS1_RS2  0x707f
+#define CSR_USTATUS 0x0
+#define CSR_UIE 0x4
+#define CSR_UTVEC 0x5
+#define CSR_USCRATCH 0x40
+#define CSR_UEPC 0x41
+#define CSR_UCAUSE 0x42
+#define CSR_UTVAL 0x43
+#define CSR_UIP 0x44
 #define CSR_FFLAGS 0x1
 #define CSR_FRM 0x2
 #define CSR_FCSR 0x3
@@ -602,7 +610,41 @@
 #define CSR_HPMCOUNTER29 0xc1d
 #define CSR_HPMCOUNTER30 0xc1e
 #define CSR_HPMCOUNTER31 0xc1f
+#define CSR_CYCLEH 0xc80
+#define CSR_TIMEH 0xc81
+#define CSR_INSTRETH 0xc82
+#define CSR_HPMCOUNTER3H 0xc83
+#define CSR_HPMCOUNTER4H 0xc84
+#define CSR_HPMCOUNTER5H 0xc85
+#define CSR_HPMCOUNTER6H 0xc86
+#define CSR_HPMCOUNTER7H 0xc87
+#define CSR_HPMCOUNTER8H 0xc88
+#define CSR_HPMCOUNTER9H 0xc89
+#define CSR_HPMCOUNTER10H 0xc8a
+#define CSR_HPMCOUNTER11H 0xc8b
+#define CSR_HPMCOUNTER12H 0xc8c
+#define CSR_HPMCOUNTER13H 0xc8d
+#define CSR_HPMCOUNTER14H 0xc8e
+#define CSR_HPMCOUNTER15H 0xc8f
+#define CSR_HPMCOUNTER16H 0xc90
+#define CSR_HPMCOUNTER17H 0xc91
+#define CSR_HPMCOUNTER18H 0xc92
+#define CSR_HPMCOUNTER19H 0xc93
+#define CSR_HPMCOUNTER20H 0xc94
+#define CSR_HPMCOUNTER21H 0xc95
+#define CSR_HPMCOUNTER22H 0xc96
+#define CSR_HPMCOUNTER23H 0xc97
+#define CSR_HPMCOUNTER24H 0xc98
+#define CSR_HPMCOUNTER25H 0xc99
+#define CSR_HPMCOUNTER26H 0xc9a
+#define CSR_HPMCOUNTER27H 0xc9b
+#define CSR_HPMCOUNTER28H 0xc9c
+#define CSR_HPMCOUNTER29H 0xc9d
+#define CSR_HPMCOUNTER30H 0xc9e
+#define CSR_HPMCOUNTER31H 0xc9f
 #define CSR_SSTATUS 0x100
+#define CSR_SEDELEG 0x102
+#define CSR_SIDELEG 0x103
 #define CSR_SIE 0x104
 #define CSR_STVEC 0x105
 #define CSR_SCOUNTEREN 0x106
@@ -612,6 +654,10 @@
 #define CSR_SBADADDR 0x143
 #define CSR_SIP 0x144
 #define CSR_SATP 0x180
+#define CSR_MVENDORID 0xf11
+#define CSR_MARCHID 0xf12
+#define CSR_MIMPID 0xf13
+#define CSR_MHARTID 0xf14
 #define CSR_MSTATUS 0x300
 #define CSR_MISA 0x301
 #define CSR_MEDELEG 0x302
@@ -644,13 +690,6 @@
 #define CSR_PMPADDR13 0x3bd
 #define CSR_PMPADDR14 0x3be
 #define CSR_PMPADDR15 0x3bf
-#define CSR_TSELECT 0x7a0
-#define CSR_TDATA1 0x7a1
-#define CSR_TDATA2 0x7a2
-#define CSR_TDATA3 0x7a3
-#define CSR_DCSR 0x7b0
-#define CSR_DPC 0x7b1
-#define CSR_DSCRATCH 0x7b2
 #define CSR_MCYCLE 0xb00
 #define CSR_MINSTRET 0xb02
 #define CSR_MHPMCOUNTER3 0xb03
@@ -682,73 +721,6 @@
 #define CSR_MHPMCOUNTER29 0xb1d
 #define CSR_MHPMCOUNTER30 0xb1e
 #define CSR_MHPMCOUNTER31 0xb1f
-#define CSR_MUCOUNTEREN 0x320
-#define CSR_MSCOUNTEREN 0x321
-#define CSR_MHPMEVENT3 0x323
-#define CSR_MHPMEVENT4 0x324
-#define CSR_MHPMEVENT5 0x325
-#define CSR_MHPMEVENT6 0x326
-#define CSR_MHPMEVENT7 0x327
-#define CSR_MHPMEVENT8 0x328
-#define CSR_MHPMEVENT9 0x329
-#define CSR_MHPMEVENT10 0x32a
-#define CSR_MHPMEVENT11 0x32b
-#define CSR_MHPMEVENT12 0x32c
-#define CSR_MHPMEVENT13 0x32d
-#define CSR_MHPMEVENT14 0x32e
-#define CSR_MHPMEVENT15 0x32f
-#define CSR_MHPMEVENT16 0x330
-#define CSR_MHPMEVENT17 0x331
-#define CSR_MHPMEVENT18 0x332
-#define CSR_MHPMEVENT19 0x333
-#define CSR_MHPMEVENT20 0x334
-#define CSR_MHPMEVENT21 0x335
-#define CSR_MHPMEVENT22 0x336
-#define CSR_MHPMEVENT23 0x337
-#define CSR_MHPMEVENT24 0x338
-#define CSR_MHPMEVENT25 0x339
-#define CSR_MHPMEVENT26 0x33a
-#define CSR_MHPMEVENT27 0x33b
-#define CSR_MHPMEVENT28 0x33c
-#define CSR_MHPMEVENT29 0x33d
-#define CSR_MHPMEVENT30 0x33e
-#define CSR_MHPMEVENT31 0x33f
-#define CSR_MVENDORID 0xf11
-#define CSR_MARCHID 0xf12
-#define CSR_MIMPID 0xf13
-#define CSR_MHARTID 0xf14
-#define CSR_CYCLEH 0xc80
-#define CSR_TIMEH 0xc81
-#define CSR_INSTRETH 0xc82
-#define CSR_HPMCOUNTER3H 0xc83
-#define CSR_HPMCOUNTER4H 0xc84
-#define CSR_HPMCOUNTER5H 0xc85
-#define CSR_HPMCOUNTER6H 0xc86
-#define CSR_HPMCOUNTER7H 0xc87
-#define CSR_HPMCOUNTER8H 0xc88
-#define CSR_HPMCOUNTER9H 0xc89
-#define CSR_HPMCOUNTER10H 0xc8a
-#define CSR_HPMCOUNTER11H 0xc8b
-#define CSR_HPMCOUNTER12H 0xc8c
-#define CSR_HPMCOUNTER13H 0xc8d
-#define CSR_HPMCOUNTER14H 0xc8e
-#define CSR_HPMCOUNTER15H 0xc8f
-#define CSR_HPMCOUNTER16H 0xc90
-#define CSR_HPMCOUNTER17H 0xc91
-#define CSR_HPMCOUNTER18H 0xc92
-#define CSR_HPMCOUNTER19H 0xc93
-#define CSR_HPMCOUNTER20H 0xc94
-#define CSR_HPMCOUNTER21H 0xc95
-#define CSR_HPMCOUNTER22H 0xc96
-#define CSR_HPMCOUNTER23H 0xc97
-#define CSR_HPMCOUNTER24H 0xc98
-#define CSR_HPMCOUNTER25H 0xc99
-#define CSR_HPMCOUNTER26H 0xc9a
-#define CSR_HPMCOUNTER27H 0xc9b
-#define CSR_HPMCOUNTER28H 0xc9c
-#define CSR_HPMCOUNTER29H 0xc9d
-#define CSR_HPMCOUNTER30H 0xc9e
-#define CSR_HPMCOUNTER31H 0xc9f
 #define CSR_MCYCLEH 0xb80
 #define CSR_MINSTRETH 0xb82
 #define CSR_MHPMCOUNTER3H 0xb83
@@ -780,6 +752,63 @@
 #define CSR_MHPMCOUNTER29H 0xb9d
 #define CSR_MHPMCOUNTER30H 0xb9e
 #define CSR_MHPMCOUNTER31H 0xb9f
+#define CSR_MHPMEVENT3 0x323
+#define CSR_MHPMEVENT4 0x324
+#define CSR_MHPMEVENT5 0x325
+#define CSR_MHPMEVENT6 0x326
+#define CSR_MHPMEVENT7 0x327
+#define CSR_MHPMEVENT8 0x328
+#define CSR_MHPMEVENT9 0x329
+#define CSR_MHPMEVENT10 0x32a
+#define CSR_MHPMEVENT11 0x32b
+#define CSR_MHPMEVENT12 0x32c
+#define CSR_MHPMEVENT13 0x32d
+#define CSR_MHPMEVENT14 0x32e
+#define CSR_MHPMEVENT15 0x32f
+#define CSR_MHPMEVENT16 0x330
+#define CSR_MHPMEVENT17 0x331
+#define CSR_MHPMEVENT18 0x332
+#define CSR_MHPMEVENT19 0x333
+#define CSR_MHPMEVENT20 0x334
+#define CSR_MHPMEVENT21 0x335
+#define CSR_MHPMEVENT22 0x336
+#define CSR_MHPMEVENT23 0x337
+#define CSR_MHPMEVENT24 0x338
+#define CSR_MHPMEVENT25 0x339
+#define CSR_MHPMEVENT26 0x33a
+#define CSR_MHPMEVENT27 0x33b
+#define CSR_MHPMEVENT28 0x33c
+#define CSR_MHPMEVENT29 0x33d
+#define CSR_MHPMEVENT30 0x33e
+#define CSR_MHPMEVENT31 0x33f
+#define CSR_TSELECT 0x7a0
+#define CSR_TDATA1 0x7a1
+#define CSR_TDATA2 0x7a2
+#define CSR_TDATA3 0x7a3
+#define CSR_DCSR 0x7b0
+#define CSR_DPC 0x7b1
+#define CSR_DSCRATCH 0x7b2
+/* These registers are present in priv spec 1.9.1, dropped in 1.10.  */
+#define CSR_HSTATUS 0x200
+#define CSR_HEDELEG 0x202
+#define CSR_HIDELEG 0x203
+#define CSR_HIE 0x204
+#define CSR_HTVEC 0x205
+#define CSR_HSCRATCH 0x240
+#define CSR_HEPC 0x241
+#define CSR_HCAUSE 0x242
+#define CSR_HBADADDR 0x243
+#define CSR_HIP 0x244
+/* CSR_MISA is 0xf10 in 1.9, but 0x301 in 1.9.1.  */
+#define CSR_MBASE 0x380
+#define CSR_MBOUND 0x381
+#define CSR_MIBASE 0x382
+#define CSR_MIBOUND 0x383
+#define CSR_MDBASE 0x384
+#define CSR_MDBOUND 0x385
+#define CSR_MUCOUNTEREN 0x320
+#define CSR_MSCOUNTEREN 0x321
+#define CSR_MHCOUNTEREN 0x322
 #define CAUSE_MISALIGNED_FETCH 0x0
 #define CAUSE_FAULT_FETCH 0x1
 #define CAUSE_ILLEGAL_INSTRUCTION 0x2
@@ -1079,6 +1108,14 @@ DECLARE_INSN(custom3_rd_rs1, MATCH_CUSTOM3_RD_RS1, MASK_CUSTOM3_RD_RS1)
 DECLARE_INSN(custom3_rd_rs1_rs2, MATCH_CUSTOM3_RD_RS1_RS2, MASK_CUSTOM3_RD_RS1_RS2)
 #endif
 #ifdef DECLARE_CSR
+DECLARE_CSR(ustatus, CSR_USTATUS)
+DECLARE_CSR(uie, CSR_UIE)
+DECLARE_CSR(utvec, CSR_UTVEC)
+DECLARE_CSR(uscratch, CSR_USCRATCH)
+DECLARE_CSR(uepc, CSR_UEPC)
+DECLARE_CSR(ucause, CSR_UCAUSE)
+DECLARE_CSR(utval, CSR_UTVAL)
+DECLARE_CSR(uip, CSR_UIP)
 DECLARE_CSR(fflags, CSR_FFLAGS)
 DECLARE_CSR(frm, CSR_FRM)
 DECLARE_CSR(fcsr, CSR_FCSR)
@@ -1114,7 +1151,41 @@ DECLARE_CSR(hpmcounter28, CSR_HPMCOUNTER28)
 DECLARE_CSR(hpmcounter29, CSR_HPMCOUNTER29)
 DECLARE_CSR(hpmcounter30, CSR_HPMCOUNTER30)
 DECLARE_CSR(hpmcounter31, CSR_HPMCOUNTER31)
+DECLARE_CSR(cycleh, CSR_CYCLEH)
+DECLARE_CSR(timeh, CSR_TIMEH)
+DECLARE_CSR(instreth, CSR_INSTRETH)
+DECLARE_CSR(hpmcounter3h, CSR_HPMCOUNTER3H)
+DECLARE_CSR(hpmcounter4h, CSR_HPMCOUNTER4H)
+DECLARE_CSR(hpmcounter5h, CSR_HPMCOUNTER5H)
+DECLARE_CSR(hpmcounter6h, CSR_HPMCOUNTER6H)
+DECLARE_CSR(hpmcounter7h, CSR_HPMCOUNTER7H)
+DECLARE_CSR(hpmcounter8h, CSR_HPMCOUNTER8H)
+DECLARE_CSR(hpmcounter9h, CSR_HPMCOUNTER9H)
+DECLARE_CSR(hpmcounter10h, CSR_HPMCOUNTER10H)
+DECLARE_CSR(hpmcounter11h, CSR_HPMCOUNTER11H)
+DECLARE_CSR(hpmcounter12h, CSR_HPMCOUNTER12H)
+DECLARE_CSR(hpmcounter13h, CSR_HPMCOUNTER13H)
+DECLARE_CSR(hpmcounter14h, CSR_HPMCOUNTER14H)
+DECLARE_CSR(hpmcounter15h, CSR_HPMCOUNTER15H)
+DECLARE_CSR(hpmcounter16h, CSR_HPMCOUNTER16H)
+DECLARE_CSR(hpmcounter17h, CSR_HPMCOUNTER17H)
+DECLARE_CSR(hpmcounter18h, CSR_HPMCOUNTER18H)
+DECLARE_CSR(hpmcounter19h, CSR_HPMCOUNTER19H)
+DECLARE_CSR(hpmcounter20h, CSR_HPMCOUNTER20H)
+DECLARE_CSR(hpmcounter21h, CSR_HPMCOUNTER21H)
+DECLARE_CSR(hpmcounter22h, CSR_HPMCOUNTER22H)
+DECLARE_CSR(hpmcounter23h, CSR_HPMCOUNTER23H)
+DECLARE_CSR(hpmcounter24h, CSR_HPMCOUNTER24H)
+DECLARE_CSR(hpmcounter25h, CSR_HPMCOUNTER25H)
+DECLARE_CSR(hpmcounter26h, CSR_HPMCOUNTER26H)
+DECLARE_CSR(hpmcounter27h, CSR_HPMCOUNTER27H)
+DECLARE_CSR(hpmcounter28h, CSR_HPMCOUNTER28H)
+DECLARE_CSR(hpmcounter29h, CSR_HPMCOUNTER29H)
+DECLARE_CSR(hpmcounter30h, CSR_HPMCOUNTER30H)
+DECLARE_CSR(hpmcounter31h, CSR_HPMCOUNTER31H)
 DECLARE_CSR(sstatus, CSR_SSTATUS)
+DECLARE_CSR(sedeleg, CSR_SEDELEG)
+DECLARE_CSR(sideleg, CSR_SIDELEG)
 DECLARE_CSR(sie, CSR_SIE)
 DECLARE_CSR(stvec, CSR_STVEC)
 DECLARE_CSR(scounteren, CSR_SCOUNTEREN)
@@ -1124,6 +1195,10 @@ DECLARE_CSR(scause, CSR_SCAUSE)
 DECLARE_CSR(sbadaddr, CSR_SBADADDR)
 DECLARE_CSR(sip, CSR_SIP)
 DECLARE_CSR(satp, CSR_SATP)
+DECLARE_CSR(mvendorid, CSR_MVENDORID)
+DECLARE_CSR(marchid, CSR_MARCHID)
+DECLARE_CSR(mimpid, CSR_MIMPID)
+DECLARE_CSR(mhartid, CSR_MHARTID)
 DECLARE_CSR(mstatus, CSR_MSTATUS)
 DECLARE_CSR(misa, CSR_MISA)
 DECLARE_CSR(medeleg, CSR_MEDELEG)
@@ -1156,13 +1231,6 @@ DECLARE_CSR(pmpaddr12, CSR_PMPADDR12)
 DECLARE_CSR(pmpaddr13, CSR_PMPADDR13)
 DECLARE_CSR(pmpaddr14, CSR_PMPADDR14)
 DECLARE_CSR(pmpaddr15, CSR_PMPADDR15)
-DECLARE_CSR(tselect, CSR_TSELECT)
-DECLARE_CSR(tdata1, CSR_TDATA1)
-DECLARE_CSR(tdata2, CSR_TDATA2)
-DECLARE_CSR(tdata3, CSR_TDATA3)
-DECLARE_CSR(dcsr, CSR_DCSR)
-DECLARE_CSR(dpc, CSR_DPC)
-DECLARE_CSR(dscratch, CSR_DSCRATCH)
 DECLARE_CSR(mcycle, CSR_MCYCLE)
 DECLARE_CSR(minstret, CSR_MINSTRET)
 DECLARE_CSR(mhpmcounter3, CSR_MHPMCOUNTER3)
@@ -1194,73 +1262,6 @@ DECLARE_CSR(mhpmcounter28, CSR_MHPMCOUNTER28)
 DECLARE_CSR(mhpmcounter29, CSR_MHPMCOUNTER29)
 DECLARE_CSR(mhpmcounter30, CSR_MHPMCOUNTER30)
 DECLARE_CSR(mhpmcounter31, CSR_MHPMCOUNTER31)
-DECLARE_CSR(mucounteren, CSR_MUCOUNTEREN)
-DECLARE_CSR(mscounteren, CSR_MSCOUNTEREN)
-DECLARE_CSR(mhpmevent3, CSR_MHPMEVENT3)
-DECLARE_CSR(mhpmevent4, CSR_MHPMEVENT4)
-DECLARE_CSR(mhpmevent5, CSR_MHPMEVENT5)
-DECLARE_CSR(mhpmevent6, CSR_MHPMEVENT6)
-DECLARE_CSR(mhpmevent7, CSR_MHPMEVENT7)
-DECLARE_CSR(mhpmevent8, CSR_MHPMEVENT8)
-DECLARE_CSR(mhpmevent9, CSR_MHPMEVENT9)
-DECLARE_CSR(mhpmevent10, CSR_MHPMEVENT10)
-DECLARE_CSR(mhpmevent11, CSR_MHPMEVENT11)
-DECLARE_CSR(mhpmevent12, CSR_MHPMEVENT12)
-DECLARE_CSR(mhpmevent13, CSR_MHPMEVENT13)
-DECLARE_CSR(mhpmevent14, CSR_MHPMEVENT14)
-DECLARE_CSR(mhpmevent15, CSR_MHPMEVENT15)
-DECLARE_CSR(mhpmevent16, CSR_MHPMEVENT16)
-DECLARE_CSR(mhpmevent17, CSR_MHPMEVENT17)
-DECLARE_CSR(mhpmevent18, CSR_MHPMEVENT18)
-DECLARE_CSR(mhpmevent19, CSR_MHPMEVENT19)
-DECLARE_CSR(mhpmevent20, CSR_MHPMEVENT20)
-DECLARE_CSR(mhpmevent21, CSR_MHPMEVENT21)
-DECLARE_CSR(mhpmevent22, CSR_MHPMEVENT22)
-DECLARE_CSR(mhpmevent23, CSR_MHPMEVENT23)
-DECLARE_CSR(mhpmevent24, CSR_MHPMEVENT24)
-DECLARE_CSR(mhpmevent25, CSR_MHPMEVENT25)
-DECLARE_CSR(mhpmevent26, CSR_MHPMEVENT26)
-DECLARE_CSR(mhpmevent27, CSR_MHPMEVENT27)
-DECLARE_CSR(mhpmevent28, CSR_MHPMEVENT28)
-DECLARE_CSR(mhpmevent29, CSR_MHPMEVENT29)
-DECLARE_CSR(mhpmevent30, CSR_MHPMEVENT30)
-DECLARE_CSR(mhpmevent31, CSR_MHPMEVENT31)
-DECLARE_CSR(mvendorid, CSR_MVENDORID)
-DECLARE_CSR(marchid, CSR_MARCHID)
-DECLARE_CSR(mimpid, CSR_MIMPID)
-DECLARE_CSR(mhartid, CSR_MHARTID)
-DECLARE_CSR(cycleh, CSR_CYCLEH)
-DECLARE_CSR(timeh, CSR_TIMEH)
-DECLARE_CSR(instreth, CSR_INSTRETH)
-DECLARE_CSR(hpmcounter3h, CSR_HPMCOUNTER3H)
-DECLARE_CSR(hpmcounter4h, CSR_HPMCOUNTER4H)
-DECLARE_CSR(hpmcounter5h, CSR_HPMCOUNTER5H)
-DECLARE_CSR(hpmcounter6h, CSR_HPMCOUNTER6H)
-DECLARE_CSR(hpmcounter7h, CSR_HPMCOUNTER7H)
-DECLARE_CSR(hpmcounter8h, CSR_HPMCOUNTER8H)
-DECLARE_CSR(hpmcounter9h, CSR_HPMCOUNTER9H)
-DECLARE_CSR(hpmcounter10h, CSR_HPMCOUNTER10H)
-DECLARE_CSR(hpmcounter11h, CSR_HPMCOUNTER11H)
-DECLARE_CSR(hpmcounter12h, CSR_HPMCOUNTER12H)
-DECLARE_CSR(hpmcounter13h, CSR_HPMCOUNTER13H)
-DECLARE_CSR(hpmcounter14h, CSR_HPMCOUNTER14H)
-DECLARE_CSR(hpmcounter15h, CSR_HPMCOUNTER15H)
-DECLARE_CSR(hpmcounter16h, CSR_HPMCOUNTER16H)
-DECLARE_CSR(hpmcounter17h, CSR_HPMCOUNTER17H)
-DECLARE_CSR(hpmcounter18h, CSR_HPMCOUNTER18H)
-DECLARE_CSR(hpmcounter19h, CSR_HPMCOUNTER19H)
-DECLARE_CSR(hpmcounter20h, CSR_HPMCOUNTER20H)
-DECLARE_CSR(hpmcounter21h, CSR_HPMCOUNTER21H)
-DECLARE_CSR(hpmcounter22h, CSR_HPMCOUNTER22H)
-DECLARE_CSR(hpmcounter23h, CSR_HPMCOUNTER23H)
-DECLARE_CSR(hpmcounter24h, CSR_HPMCOUNTER24H)
-DECLARE_CSR(hpmcounter25h, CSR_HPMCOUNTER25H)
-DECLARE_CSR(hpmcounter26h, CSR_HPMCOUNTER26H)
-DECLARE_CSR(hpmcounter27h, CSR_HPMCOUNTER27H)
-DECLARE_CSR(hpmcounter28h, CSR_HPMCOUNTER28H)
-DECLARE_CSR(hpmcounter29h, CSR_HPMCOUNTER29H)
-DECLARE_CSR(hpmcounter30h, CSR_HPMCOUNTER30H)
-DECLARE_CSR(hpmcounter31h, CSR_HPMCOUNTER31H)
 DECLARE_CSR(mcycleh, CSR_MCYCLEH)
 DECLARE_CSR(minstreth, CSR_MINSTRETH)
 DECLARE_CSR(mhpmcounter3h, CSR_MHPMCOUNTER3H)
@@ -1292,8 +1293,67 @@ DECLARE_CSR(mhpmcounter28h, CSR_MHPMCOUNTER28H)
 DECLARE_CSR(mhpmcounter29h, CSR_MHPMCOUNTER29H)
 DECLARE_CSR(mhpmcounter30h, CSR_MHPMCOUNTER30H)
 DECLARE_CSR(mhpmcounter31h, CSR_MHPMCOUNTER31H)
+DECLARE_CSR(mhpmevent3, CSR_MHPMEVENT3)
+DECLARE_CSR(mhpmevent4, CSR_MHPMEVENT4)
+DECLARE_CSR(mhpmevent5, CSR_MHPMEVENT5)
+DECLARE_CSR(mhpmevent6, CSR_MHPMEVENT6)
+DECLARE_CSR(mhpmevent7, CSR_MHPMEVENT7)
+DECLARE_CSR(mhpmevent8, CSR_MHPMEVENT8)
+DECLARE_CSR(mhpmevent9, CSR_MHPMEVENT9)
+DECLARE_CSR(mhpmevent10, CSR_MHPMEVENT10)
+DECLARE_CSR(mhpmevent11, CSR_MHPMEVENT11)
+DECLARE_CSR(mhpmevent12, CSR_MHPMEVENT12)
+DECLARE_CSR(mhpmevent13, CSR_MHPMEVENT13)
+DECLARE_CSR(mhpmevent14, CSR_MHPMEVENT14)
+DECLARE_CSR(mhpmevent15, CSR_MHPMEVENT15)
+DECLARE_CSR(mhpmevent16, CSR_MHPMEVENT16)
+DECLARE_CSR(mhpmevent17, CSR_MHPMEVENT17)
+DECLARE_CSR(mhpmevent18, CSR_MHPMEVENT18)
+DECLARE_CSR(mhpmevent19, CSR_MHPMEVENT19)
+DECLARE_CSR(mhpmevent20, CSR_MHPMEVENT20)
+DECLARE_CSR(mhpmevent21, CSR_MHPMEVENT21)
+DECLARE_CSR(mhpmevent22, CSR_MHPMEVENT22)
+DECLARE_CSR(mhpmevent23, CSR_MHPMEVENT23)
+DECLARE_CSR(mhpmevent24, CSR_MHPMEVENT24)
+DECLARE_CSR(mhpmevent25, CSR_MHPMEVENT25)
+DECLARE_CSR(mhpmevent26, CSR_MHPMEVENT26)
+DECLARE_CSR(mhpmevent27, CSR_MHPMEVENT27)
+DECLARE_CSR(mhpmevent28, CSR_MHPMEVENT28)
+DECLARE_CSR(mhpmevent29, CSR_MHPMEVENT29)
+DECLARE_CSR(mhpmevent30, CSR_MHPMEVENT30)
+DECLARE_CSR(mhpmevent31, CSR_MHPMEVENT31)
+DECLARE_CSR(tselect, CSR_TSELECT)
+DECLARE_CSR(tdata1, CSR_TDATA1)
+DECLARE_CSR(tdata2, CSR_TDATA2)
+DECLARE_CSR(tdata3, CSR_TDATA3)
+DECLARE_CSR(dcsr, CSR_DCSR)
+DECLARE_CSR(dpc, CSR_DPC)
+DECLARE_CSR(dscratch, CSR_DSCRATCH)
+/* These registers are present in priv spec 1.9.1, dropped in 1.10.  */
+DECLARE_CSR(hstatus, CSR_HSTATUS)
+DECLARE_CSR(hedeleg, CSR_HEDELEG)
+DECLARE_CSR(hideleg, CSR_HIDELEG)
+DECLARE_CSR(hie, CSR_HIE)
+DECLARE_CSR(htvec, CSR_HTVEC)
+DECLARE_CSR(hscratch, CSR_HSCRATCH)
+DECLARE_CSR(hepc, CSR_HEPC)
+DECLARE_CSR(hcause, CSR_HCAUSE)
+DECLARE_CSR(hbadaddr, CSR_HBADADDR)
+DECLARE_CSR(hip, CSR_HIP)
+DECLARE_CSR(mbase, CSR_MBASE)
+DECLARE_CSR(mbound, CSR_MBOUND)
+DECLARE_CSR(mibase, CSR_MIBASE)
+DECLARE_CSR(mibound, CSR_MIBOUND)
+DECLARE_CSR(mdbase, CSR_MDBASE)
+DECLARE_CSR(mdbound, CSR_MDBOUND)
+DECLARE_CSR(mucounteren, CSR_MUCOUNTEREN)
+DECLARE_CSR(mscounteren, CSR_MSCOUNTEREN)
+DECLARE_CSR(mhcounteren, CSR_MHCOUNTEREN)
 #endif
 #ifdef DECLARE_CSR_ALIAS
+/* Ubadaddr is 0x043 in 1.9.1, but 0x043 is utval in 1.10.  */
+DECLARE_CSR_ALIAS(ubadaddr, CSR_UTVAL)
+/* Sptbr is 0x180 in 1.9.1, but 0x180 is satp in 1.10.  */
 DECLARE_CSR_ALIAS(sptbr, CSR_SATP)
 #endif
 #ifdef DECLARE_CAUSE