From: Eddie Hung <eddie@fpgeh.com>
Date: Fri, 3 May 2019 22:05:57 +0000 (-0700)
Subject: Merge remote-tracking branch 'origin/master' into clifford/specify
X-Git-Tag: yosys-0.9~141^2~8
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=d9c4644e88b916d1eadfd401abf297c0995b6462;p=yosys.git

Merge remote-tracking branch 'origin/master' into clifford/specify
---

d9c4644e88b916d1eadfd401abf297c0995b6462
diff --cc frontends/verilog/verilog_frontend.cc
index 8202ab9d7,9e624d355..01e589efb
--- a/frontends/verilog/verilog_frontend.cc
+++ b/frontends/verilog/verilog_frontend.cc
@@@ -242,12 -237,11 +242,10 @@@ struct VerilogFrontend : public Fronten
  		formal_mode = false;
  		norestrict_mode = false;
  		assume_asserts_mode = false;
 -		noblackbox_mode = false;
  		lib_mode = false;
 -		nowb_mode = false;
 +		specify_mode = false;
  		default_nettype_wire = true;
  
- 		log_header(design, "Executing Verilog-2005 frontend.\n");
- 
  		args.insert(args.begin()+1, verilog_defaults.begin(), verilog_defaults.end());
  
  		size_t argidx;