From: Eddie Hung <eddie@fpgeh.com>
Date: Tue, 23 Apr 2019 20:42:35 +0000 (-0700)
Subject: Move clean from aigerparse to abc9
X-Git-Tag: working-ls180~1237^2~161
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=d9c915042a610672e313f976cdbcbf9a814c380d;p=yosys.git

Move clean from aigerparse to abc9
---

diff --git a/frontends/aiger/aigerparse.cc b/frontends/aiger/aigerparse.cc
index b9ab6fc09..904a1079d 100644
--- a/frontends/aiger/aigerparse.cc
+++ b/frontends/aiger/aigerparse.cc
@@ -598,8 +598,6 @@ next_line:
     module->fixup_ports();
     design->add(module);
 
-    Pass::call(design, "clean");
-
     for (auto cell : module->cells().to_vector()) {
         if (cell->type != "$lut") continue;
         auto y_port = cell->getPort("\\Y").as_bit();
diff --git a/passes/techmap/abc9.cc b/passes/techmap/abc9.cc
index 67d0981f4..2aa19b348 100644
--- a/passes/techmap/abc9.cc
+++ b/passes/techmap/abc9.cc
@@ -548,6 +548,7 @@ void abc9_module(RTLIL::Design *design, RTLIL::Module *current_module, std::stri
 		RTLIL::Module *mapped_mod = mapped_design->modules_["\\netlist"];
 		if (mapped_mod == NULL)
 			log_error("ABC output file does not contain a module `netlist'.\n");
+		Pass::call(mapped_design, "clean");
 
 		pool<RTLIL::SigBit> output_bits;
 		for (auto &it : mapped_mod->wires_) {