From: Samuel Pitoiset Date: Thu, 8 Nov 2018 13:00:36 +0000 (+0100) Subject: radv: clean up setting partial_es_wave for distributed tess on VI X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=d9d14346c2ba66bfef7ca120ccbcd3201ca32359;p=mesa.git radv: clean up setting partial_es_wave for distributed tess on VI Only needed when the pipeline actually uses tessellation. I don't think that changes anything, except improving readability. Signed-off-by: Samuel Pitoiset Reviewed-by: Bas Nieuwenhuizen --- diff --git a/src/amd/vulkan/radv_pipeline.c b/src/amd/vulkan/radv_pipeline.c index bced19573c1..f9993830182 100644 --- a/src/amd/vulkan/radv_pipeline.c +++ b/src/amd/vulkan/radv_pipeline.c @@ -3371,14 +3371,8 @@ radv_compute_ia_multi_vgt_param_helpers(struct radv_pipeline *pipeline, else ia_multi_vgt_param.primgroup_size = 128; /* recommended without a GS */ - ia_multi_vgt_param.partial_es_wave = false; - if (pipeline->device->has_distributed_tess) { - if (radv_pipeline_has_gs(pipeline)) { - if (device->physical_device->rad_info.chip_class <= VI) - ia_multi_vgt_param.partial_es_wave = true; - } - } /* GS requirement. */ + ia_multi_vgt_param.partial_es_wave = false; if (radv_pipeline_has_gs(pipeline) && device->physical_device->rad_info.chip_class <= VI) if (SI_GS_PER_ES / ia_multi_vgt_param.primgroup_size >= pipeline->device->gs_table_depth - 3) ia_multi_vgt_param.partial_es_wave = true; @@ -3425,6 +3419,9 @@ radv_compute_ia_multi_vgt_param_helpers(struct radv_pipeline *pipeline, /* Needed for 028B6C_DISTRIBUTION_MODE != 0 */ if (device->has_distributed_tess) { if (radv_pipeline_has_gs(pipeline)) { + if (device->physical_device->rad_info.chip_class <= VI) + ia_multi_vgt_param.partial_es_wave = true; + if (device->physical_device->rad_info.family == CHIP_TONGA || device->physical_device->rad_info.family == CHIP_FIJI || device->physical_device->rad_info.family == CHIP_POLARIS10 ||