From: Clifford Wolf Date: Tue, 25 Oct 2016 21:21:37 +0000 (+0200) Subject: Bugfix in fsm_map for FSMs without reset state X-Git-Tag: yosys-0.7~11 X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=d9d38eeedba7d650ff80e2b364f2f40e9ff1673b;p=yosys.git Bugfix in fsm_map for FSMs without reset state --- diff --git a/passes/fsm/fsm_map.cc b/passes/fsm/fsm_map.cc index 5b32ed599..c42303752 100644 --- a/passes/fsm/fsm_map.cc +++ b/passes/fsm/fsm_map.cc @@ -272,7 +272,8 @@ static void map_fsm(RTLIL::Cell *fsm_cell, RTLIL::Module *module) } else { - RTLIL::SigSpec sig_a, sig_b, sig_s; + RTLIL::SigSpec sig_a(RTLIL::State::Sx, next_state_wire->width); + RTLIL::SigSpec sig_b, sig_s; int reset_state = fsm_data.reset_state; if (reset_state < 0) reset_state = 0;