From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Tue, 16 Jun 2020 12:41:17 +0000 (+0100)
Subject: add test instruction memory SRAM
X-Git-Tag: div_pipeline~365
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=d9e947e2b91e592732fef8d8a4a9412c4503c79b;p=soc.git

add test instruction memory SRAM
---

diff --git a/src/soc/regfile/regfiles.py b/src/soc/regfile/regfiles.py
index 1d5a2213..4a8f5a3f 100644
--- a/src/soc/regfile/regfiles.py
+++ b/src/soc/regfile/regfiles.py
@@ -55,6 +55,9 @@ class FastRegs(RegFileArray):
     * 3R2W
     * Array-based unary-indexed (not binary-indexed)
     * write-through capability (read on same cycle as write)
+
+    Note: d_wr1 and d_rd1 are for use by the decoder, to get at the PC.
+    will probably have to also add one so it can get at the MSR as well.
     """
     PC = 0
     MSR = 1
@@ -68,11 +71,13 @@ class FastRegs(RegFileArray):
         self.w_ports = {'nia': self.write_port("dest1"),
                         'msr': self.write_port("dest2"),
                         'spr1': self.write_port("dest3"),
-                        'spr2': self.write_port("dest3")}
+                        'spr2': self.write_port("dest4"),
+                        'd_wr1': self.write_port("d_wr1")}
         self.r_ports = {'cia': self.read_port("src1"),
                         'msr': self.read_port("src2"),
                         'spr1': self.read_port("src3"),
-                        'spr2': self.read_port("src3")}
+                        'spr2': self.read_port("src4"),
+                        'd_rd1': self.read_port("d_rd1")}
 
 
 # CR Regfile
diff --git a/src/soc/simple/core.py b/src/soc/simple/core.py
index 5edc508b..68c30790 100644
--- a/src/soc/simple/core.py
+++ b/src/soc/simple/core.py
@@ -30,6 +30,7 @@ from soc.regfile.regfiles import RegFiles
 from soc.decoder.power_decoder import create_pdecode
 from soc.decoder.power_decoder2 import PowerDecode2
 from soc.experiment.l0_cache import TstL0CacheBuffer # test only
+from soc.experiment.testmem import TestMemory # test only for instructions
 import operator
 
 
@@ -51,14 +52,25 @@ def sort_fuspecs(fuspecs):
 
 
 class NonProductionCore(Elaboratable):
-    def __init__(self, addrwid=6):
+    def __init__(self, addrwid=6, idepth=16):
+        # single LD/ST funnel for memory access
         self.l0 = TstL0CacheBuffer(n_units=1, regwid=64, addrwid=addrwid)
         pi = self.l0.l0.dports[0].pi
 
+        # Instruction memory
+        self.imem = TestMemory(32, idepth)
+
+        # function units (only one each)
         self.fus = AllFunctionUnits(pilist=[pi], addrwid=addrwid)
+
+        # register files (yes plural)
         self.regs = RegFiles()
+
+        # instruction decoder
         self.pdecode = pdecode = create_pdecode()
         self.pdecode2 = PowerDecode2(pdecode)   # instruction decoder
+
+        # issue/valid/busy signalling
         self.ivalid_i = self.pdecode2.e.valid   # instruction is valid
         self.issue_i = Signal(reset_less=True)
         self.busy_o = Signal(reset_less=True)
@@ -69,6 +81,7 @@ class NonProductionCore(Elaboratable):
         m.submodules.pdecode2 = dec2 = self.pdecode2
         m.submodules.fus = self.fus
         m.submodules.l0 = l0 = self.l0
+        m.submodules.imem = imem = self.imem
         self.regs.elaborate_into(m, platform)
         regs = self.regs
         fus = self.fus.fus