From: Jason Ekstrand Date: Thu, 15 Jun 2017 05:28:25 +0000 (-0700) Subject: i965/barrier: Do the correct flushes for framebuffer access X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=d9ed4f6c32b4cb1d7e0f41b1f342c336e70c0af4;p=mesa.git i965/barrier: Do the correct flushes for framebuffer access Framebuffer access includes framebuffer reads so we need to invalidate the texture cache. We do not, however, need to flush the depth cache because you cannot do bind a depth texture as an image. Reviewed-by: Topi Pohjolainen Reviewed-by: Kenneth Graunke --- diff --git a/src/mesa/drivers/dri/i965/brw_program.c b/src/mesa/drivers/dri/i965/brw_program.c index 3743fa9b5eb..c11ac871e58 100644 --- a/src/mesa/drivers/dri/i965/brw_program.c +++ b/src/mesa/drivers/dri/i965/brw_program.c @@ -274,7 +274,7 @@ brw_memory_barrier(struct gl_context *ctx, GLbitfield barriers) PIPE_CONTROL_RENDER_TARGET_FLUSH); if (barriers & GL_FRAMEBUFFER_BARRIER_BIT) - bits |= (PIPE_CONTROL_DEPTH_CACHE_FLUSH | + bits |= (PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE | PIPE_CONTROL_RENDER_TARGET_FLUSH); /* Typed surface messages are handled by the render cache on IVB, so we