From: Jason Lowe-Power Date: Fri, 9 Mar 2018 20:08:49 +0000 (-0800) Subject: learning_gem5: Ruby random tester files for MSI X-Git-Tag: v19.0.0.0~2209 X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=d9f9b80dc9b7f1d892f9b977a1342e98ebc75b00;p=gem5.git learning_gem5: Ruby random tester files for MSI Adds a pair of scripts to run the Ruby random tester with the MSI protocol. This code follows Learning gem5 Part 3. http://learning.gem5.org/book/part3/index.html Change-Id: I15550a36618546f0354163b0216cf771f434ed84 Signed-off-by: Jason Lowe-Power Reviewed-on: https://gem5-review.googlesource.com/8944 Reviewed-by: Nikos Nikoleris --- diff --git a/configs/learning_gem5/part3/ruby_test.py b/configs/learning_gem5/part3/ruby_test.py new file mode 100644 index 000000000..692a87e62 --- /dev/null +++ b/configs/learning_gem5/part3/ruby_test.py @@ -0,0 +1,84 @@ +# -*- coding: utf-8 -*- +# Copyright (c) 2015 Jason Power +# All rights reserved. +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions are +# met: redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer; +# redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in the +# documentation and/or other materials provided with the distribution; +# neither the name of the copyright holders nor the names of its +# contributors may be used to endorse or promote products derived from +# this software without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# +# Authors: Jason Lowe-Power + +""" This file creates a system with Ruby caches and runs the ruby random tester +See Part 3 in the Learning gem5 book: learning.gem5.org/book/part3 + +IMPORTANT: If you modify this file, it's likely that the Learning gem5 book + also needs to be updated. For now, email Jason + +""" +from __future__ import print_function + +# import the m5 (gem5) library created when gem5 is built +import m5 +# import all of the SimObjects +from m5.objects import * + +from test_caches import TestCacheSystem + +# create the system we are going to simulate +system = System() + +# Set the clock fequency of the system (and all of its children) +system.clk_domain = SrcClockDomain() +system.clk_domain.clock = '1GHz' +system.clk_domain.voltage_domain = VoltageDomain() + +# Set up the system +system.mem_mode = 'timing' # Use timing accesses +system.mem_ranges = [AddrRange('512MB')] # Create an address range + +# Create the tester +system.tester = RubyTester(checks_to_complete = 100, + wakeup_frequency = 10, + num_cpus = 2) + +# Create a DDR3 memory controller and connect it to the membus +system.mem_ctrl = DDR3_1600_8x8() +system.mem_ctrl.range = system.mem_ranges[0] + +# Create the Ruby System +system.caches = TestCacheSystem() +system.caches.setup(system, system.tester, [system.mem_ctrl]) + +# set up the root SimObject and start the simulation +root = Root(full_system = False, system = system) + +# Not much point in this being higher than the L1 latency +m5.ticks.setGlobalFrequency('1ns') + +# instantiate all of the objects we've created above +m5.instantiate() + +print("Beginning simulation!") +exit_event = m5.simulate() +print('Exiting @ tick {} because {}'.format( + m5.curTick(), exit_event.getCause()) + ) diff --git a/configs/learning_gem5/part3/test_caches.py b/configs/learning_gem5/part3/test_caches.py new file mode 100644 index 000000000..3721f4a6b --- /dev/null +++ b/configs/learning_gem5/part3/test_caches.py @@ -0,0 +1,111 @@ +# -*- coding: utf-8 -*- +# Copyright (c) 2017 Jason Power +# All rights reserved. +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions are +# met: redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer; +# redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in the +# documentation and/or other materials provided with the distribution; +# neither the name of the copyright holders nor the names of its +# contributors may be used to endorse or promote products derived from +# this software without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# +# Authors: Jason Power + +""" This file creates a set of Ruby caches, the Ruby network, and a simple +point-to-point topology for the RubyRandomTester to use. +See Part 3 in the Learning gem5 book: learning.gem5.org/book/part3 + +IMPORTANT: If you modify this file, it's likely that the Learning gem5 book + also needs to be updated. For now, email Jason + +""" + +from m5.defines import buildEnv +from m5.util import fatal + +from m5.objects import * + +from msi_caches import L1Cache, DirController, MyNetwork + +class TestCacheSystem(RubySystem): + + def __init__(self): + if buildEnv['PROTOCOL'] != 'MSI': + fatal("This system assumes MSI from learning gem5!") + + super(TestCacheSystem, self).__init__() + + def setup(self, system, tester, mem_ctrls): + """Set up the Ruby cache subsystem. Note: This can't be done in the + constructor because many of these items require a pointer to the + ruby system (self). This causes infinite recursion in initialize() + if we do this in the __init__. + Setting up for running the RubyRandomTester is a little different + than when we're using CPUs. + """ + num_testers = tester.num_cpus + + # Ruby's global network. + self.network = MyNetwork(self) + + # MSI uses 3 virtual networks + self.number_of_virtual_networks = 3 + self.network.number_of_virtual_networks = 3 + + self.controllers = \ + [L1Cache(system, self, self) for i in range(num_testers)] + \ + [DirController(self, system.mem_ranges, mem_ctrls)] + + self.sequencers = [RubySequencer(version = i, + # I/D cache is combined and grab from ctrl + icache = self.controllers[i].cacheMemory, + dcache = self.controllers[i].cacheMemory, + clk_domain = self.clk_domain, + ) for i in range(num_testers)] + + for i,c in enumerate(self.controllers[0:len(self.sequencers)]): + c.sequencer = self.sequencers[i] + + self.num_of_sequencers = len(self.sequencers) + + # Create the network and connect the controllers. + # NOTE: This is quite different if using Garnet! + self.network.connectControllers(self.controllers) + self.network.setup_buffers() + + # Set up a proxy port for the system_port. Used for load binaries and + # other functional-only things. + self.sys_port_proxy = RubyPortProxy() + system.system_port = self.sys_port_proxy.slave + + # Connect up the sequencers to the random tester + for seq in self.sequencers: + if seq.support_data_reqs and seq.support_inst_reqs: + tester.cpuInstDataPort = seq.slave + elif seq.support_data_reqs: + tester.cpuDataPort = seq.slave + elif seq.support_inst_reqs: + tester.cpuInstDataPort = seq.slave + + # Do not automatically retry stalled Ruby requests + seq.no_retry_on_stall = True + + # Tell each sequencer this is the ruby tester so that it + # copies the subblock back to the checker + seq.using_ruby_tester = True