From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Sun, 31 May 2020 12:04:13 +0000 (+0100)
Subject: more debug statements
X-Git-Tag: div_pipeline~720
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=d9fc84af5465b023eb6c8d60bc367d27894a6974;p=soc.git

more debug statements
---

diff --git a/src/soc/fu/compunits/test/test_alu_compunit.py b/src/soc/fu/compunits/test/test_alu_compunit.py
index b5d55a4b..ac635363 100644
--- a/src/soc/fu/compunits/test/test_alu_compunit.py
+++ b/src/soc/fu/compunits/test/test_alu_compunit.py
@@ -17,10 +17,11 @@ from soc.experiment.compalu_multi import find_ok # hack
 import random
 
 def set_cu_input(cu, idx, data):
+    rdop = cu.get_in_name(idx)
     yield cu.src_i[idx].eq(data)
     while True:
         rd_rel_o = yield cu.rd.rel[idx]
-        print ("rd_rel %d wait HI" % idx, rd_rel_o)
+        print ("rd_rel %d wait HI" % idx, rd_rel_o, rdop, hex(data))
         if rd_rel_o:
             break
         yield
@@ -54,9 +55,11 @@ def get_cu_output(cu, idx, code):
             break
         yield
     yield cu.wr.go[idx].eq(1)
-    yield
+    yield Settle()
     result = yield cu.dest[idx]
+    yield
     yield cu.wr.go[idx].eq(0)
+    print ("result", repr(code), idx, wrop, wrok, hex(result))
     return result