From: Eddie Hung <eddie@fpgeh.com>
Date: Tue, 20 Aug 2019 18:57:52 +0000 (-0700)
Subject: Merge remote-tracking branch 'origin/master' into eddie/synth_xilinx
X-Git-Tag: working-ls180~1122^2
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=d9fe4cccbf3cc03fa57b177fd13c6e900a2134f7;p=yosys.git

Merge remote-tracking branch 'origin/master' into eddie/synth_xilinx
---

d9fe4cccbf3cc03fa57b177fd13c6e900a2134f7
diff --cc CHANGELOG
index b82a62495,291c8d249..3bcb71b22
--- a/CHANGELOG
+++ b/CHANGELOG
@@@ -14,11 -14,14 +14,18 @@@ Yosys 0.9 .. Yosys 0.9-de
      - Added "synth -abc9" (experimental)
      - Added "script -scriptwire
      - "synth_xilinx" to now infer wide multiplexers (-widemux <min> to enable)
 +    - Renamed labels/options in synth_ice40 (e.g. dram -> map_lutram; -nodram -> -nolutram)
 +    - Renamed labels/options in synth_ecp5 (e.g. dram -> map_lutram; -nodram -> -nolutram)
 +    - Renamed labels in synth_intel (e.g. bram -> map_bram)
 +    - Renamed labels/options in synth_xilinx (e.g. dram -> map_lutram; -nodram -> -nolutram)
- 
+     - Added automatic gzip decompression for frontends
+     - Added $_NMUX_ cell type
+     - Added automatic gzip compression (based on filename extension) for backends
+     - Improve attribute and parameter encoding in JSON to avoid ambiguities between
+       bit vectors and strings containing [01xz]*
+     - Added "opt_share" pass, run as part of "opt -full"
+     - Added "ice40_wrapcarry" to encapsulate SB_LUT+SB_CARRY pairs for techmapping
+     - Removed "ice40_unlut"
  
  Yosys 0.8 .. Yosys 0.8-dev
  --------------------------