From: Benjamin Herrenschmidt Date: Fri, 24 Sep 2021 04:24:37 +0000 (+1000) Subject: Add support for QMTech Wukong v2 board X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=da0189af1ee53b7ecf9f6a34e0fd69b3b064849e;p=microwatt.git Add support for QMTech Wukong v2 board For now only the V2 of the board (slightly different pinout) and only the A100T variant. I also haven't added GPIOs or anything else on the PMODs really. Signed-off-by: Benjamin Herrenschmidt --- diff --git a/fpga/top-wukong-v2.vhdl b/fpga/top-wukong-v2.vhdl new file mode 100644 index 0000000..9ade110 --- /dev/null +++ b/fpga/top-wukong-v2.vhdl @@ -0,0 +1,579 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +library unisim; +use unisim.vcomponents.all; + +library work; +use work.wishbone_types.all; + +entity toplevel is + generic ( + MEMORY_SIZE : integer := 16384; + RAM_INIT_FILE : string := "firmware.hex"; + RESET_LOW : boolean := true; + CLK_FREQUENCY : positive := 100000000; + HAS_FPU : boolean := true; + HAS_BTC : boolean := true; + HAS_SHORT_MULT : boolean := false; + USE_LITEDRAM : boolean := false; + NO_BRAM : boolean := false; + DISABLE_FLATTEN_CORE : boolean := false; + SPI_FLASH_OFFSET : integer := 4194304; + SPI_FLASH_DEF_CKDV : natural := 1; + SPI_FLASH_DEF_QUAD : boolean := true; + LOG_LENGTH : natural := 512; + USE_LITEETH : boolean := false; + UART_IS_16550 : boolean := true; + HAS_UART1 : boolean := false; + USE_LITESDCARD : boolean := false; + HAS_GPIO : boolean := false; + NGPIO : natural := 32 + ); + port( + ext_clk : in std_ulogic; + ext_rst_n : in std_ulogic; + + -- UART0 signals: + uart_main_tx : out std_ulogic; + uart_main_rx : in std_ulogic; + + -- LEDs + led0_n : out std_ulogic; + led1_n : out std_ulogic; + + -- SPI + spi_flash_cs_n : out std_ulogic; + spi_flash_mosi : inout std_ulogic; + spi_flash_miso : inout std_ulogic; + spi_flash_wp_n : inout std_ulogic; + spi_flash_hold_n : inout std_ulogic; + + -- Ethernet + eth_clocks_tx : in std_ulogic; + eth_clocks_gtx : out std_ulogic; + eth_clocks_rx : in std_ulogic; + eth_rst_n : out std_ulogic; + eth_mdio : inout std_ulogic; + eth_mdc : out std_ulogic; + eth_rx_dv : in std_ulogic; + eth_rx_er : in std_ulogic; + eth_rx_data : in std_ulogic_vector(7 downto 0); + eth_tx_en : out std_ulogic; + eth_tx_er : out std_ulogic; + eth_tx_data : out std_ulogic_vector(7 downto 0); + eth_col : in std_ulogic; + eth_crs : in std_ulogic; + + -- SD card + sdcard_data : inout std_ulogic_vector(3 downto 0); + sdcard_cmd : inout std_ulogic; + sdcard_clk : out std_ulogic; + sdcard_cd : in std_ulogic; + + -- DRAM wires + ddram_a : out std_ulogic_vector(13 downto 0); + ddram_ba : out std_ulogic_vector(2 downto 0); + ddram_ras_n : out std_ulogic; + ddram_cas_n : out std_ulogic; + ddram_we_n : out std_ulogic; + ddram_dm : out std_ulogic_vector(1 downto 0); + ddram_dq : inout std_ulogic_vector(15 downto 0); + ddram_dqs_p : inout std_ulogic_vector(1 downto 0); + ddram_dqs_n : inout std_ulogic_vector(1 downto 0); + ddram_clk_p : out std_ulogic; + ddram_clk_n : out std_ulogic; + ddram_cke : out std_ulogic; + ddram_odt : out std_ulogic; + ddram_reset_n : out std_ulogic + ); +end entity toplevel; + +architecture behaviour of toplevel is + + -- Reset signals: + signal soc_rst : std_ulogic; + signal pll_rst : std_ulogic; + + -- Internal clock signals: + signal system_clk : std_ulogic; + signal system_clk_locked : std_ulogic; + + -- External IOs from the SoC + signal wb_ext_io_in : wb_io_master_out; + signal wb_ext_io_out : wb_io_slave_out; + signal wb_ext_is_dram_csr : std_ulogic; + signal wb_ext_is_dram_init : std_ulogic; + signal wb_ext_is_eth : std_ulogic; + signal wb_ext_is_sdcard : std_ulogic; + + -- DRAM main data wishbone connection + signal wb_dram_in : wishbone_master_out; + signal wb_dram_out : wishbone_slave_out; + + -- DRAM control wishbone connection + signal wb_dram_ctrl_out : wb_io_slave_out := wb_io_slave_out_init; + + -- LiteEth connection + signal ext_irq_eth : std_ulogic; + signal wb_eth_out : wb_io_slave_out := wb_io_slave_out_init; + + -- LiteSDCard connection + signal ext_irq_sdcard : std_ulogic := '0'; + signal wb_sdcard_out : wb_io_slave_out := wb_io_slave_out_init; + signal wb_sddma_out : wb_io_master_out := wb_io_master_out_init; + signal wb_sddma_in : wb_io_slave_out; + signal wb_sddma_nr : wb_io_master_out; + signal wb_sddma_ir : wb_io_slave_out; + -- for conversion from non-pipelined wishbone to pipelined + signal wb_sddma_stb_sent : std_ulogic; + + -- Control/status + signal core_alt_reset : std_ulogic; + + -- SPI flash + signal spi_sck : std_ulogic; + signal spi_cs_n : std_ulogic; + signal spi_sdat_o : std_ulogic_vector(3 downto 0); + signal spi_sdat_oe : std_ulogic_vector(3 downto 0); + signal spi_sdat_i : std_ulogic_vector(3 downto 0); + + -- Fixup various memory sizes based on generics + function get_bram_size return natural is + begin + if USE_LITEDRAM and NO_BRAM then + return 0; + else + return MEMORY_SIZE; + end if; + end function; + + function get_payload_size return natural is + begin + if USE_LITEDRAM and NO_BRAM then + return MEMORY_SIZE; + else + return 0; + end if; + end function; + + constant BRAM_SIZE : natural := get_bram_size; + constant PAYLOAD_SIZE : natural := get_payload_size; +begin + + -- Main SoC + soc0: entity work.soc + generic map( + MEMORY_SIZE => BRAM_SIZE, + RAM_INIT_FILE => RAM_INIT_FILE, + SIM => false, + CLK_FREQ => CLK_FREQUENCY, + HAS_FPU => HAS_FPU, + HAS_BTC => HAS_BTC, + HAS_SHORT_MULT => HAS_SHORT_MULT, + HAS_DRAM => USE_LITEDRAM, + DRAM_SIZE => 256 * 1024 * 1024, + DRAM_INIT_SIZE => PAYLOAD_SIZE, + DISABLE_FLATTEN_CORE => DISABLE_FLATTEN_CORE, + HAS_SPI_FLASH => true, + SPI_FLASH_DLINES => 4, + SPI_FLASH_OFFSET => SPI_FLASH_OFFSET, + SPI_FLASH_DEF_CKDV => SPI_FLASH_DEF_CKDV, + SPI_FLASH_DEF_QUAD => SPI_FLASH_DEF_QUAD, + LOG_LENGTH => LOG_LENGTH, + HAS_LITEETH => USE_LITEETH, + UART0_IS_16550 => UART_IS_16550, + HAS_UART1 => HAS_UART1, + HAS_SD_CARD => USE_LITESDCARD, + HAS_GPIO => HAS_GPIO, + NGPIO => NGPIO + ) + port map ( + -- System signals + system_clk => system_clk, + rst => soc_rst, + + -- UART signals + uart0_txd => uart_main_tx, + uart0_rxd => uart_main_rx, + + -- SPI signals + spi_flash_sck => spi_sck, + spi_flash_cs_n => spi_cs_n, + spi_flash_sdat_o => spi_sdat_o, + spi_flash_sdat_oe => spi_sdat_oe, + spi_flash_sdat_i => spi_sdat_i, + + -- External interrupts + ext_irq_eth => ext_irq_eth, + ext_irq_sdcard => ext_irq_sdcard, + + -- DRAM wishbone + wb_dram_in => wb_dram_in, + wb_dram_out => wb_dram_out, + + -- IO wishbone + wb_ext_io_in => wb_ext_io_in, + wb_ext_io_out => wb_ext_io_out, + wb_ext_is_dram_csr => wb_ext_is_dram_csr, + wb_ext_is_dram_init => wb_ext_is_dram_init, + wb_ext_is_eth => wb_ext_is_eth, + wb_ext_is_sdcard => wb_ext_is_sdcard, + + -- DMA wishbone + wishbone_dma_in => wb_sddma_in, + wishbone_dma_out => wb_sddma_out, + + alt_reset => core_alt_reset + ); + + -- SPI Flash + spi_flash_cs_n <= spi_cs_n; + spi_flash_mosi <= spi_sdat_o(0) when spi_sdat_oe(0) = '1' else 'Z'; + spi_flash_miso <= spi_sdat_o(1) when spi_sdat_oe(1) = '1' else 'Z'; + spi_flash_wp_n <= spi_sdat_o(2) when spi_sdat_oe(2) = '1' else 'Z'; + spi_flash_hold_n <= spi_sdat_o(3) when spi_sdat_oe(3) = '1' else 'Z'; + spi_sdat_i(0) <= spi_flash_mosi; + spi_sdat_i(1) <= spi_flash_miso; + spi_sdat_i(2) <= spi_flash_wp_n; + spi_sdat_i(3) <= spi_flash_hold_n; + + STARTUPE2_INST: STARTUPE2 + port map ( + CLK => '0', + GSR => '0', + GTS => '0', + KEYCLEARB => '0', + PACK => '0', + USRCCLKO => spi_sck, + USRCCLKTS => '0', + USRDONEO => '1', + USRDONETS => '0' + ); + + nodram: if not USE_LITEDRAM generate + signal ddram_clk_dummy : std_ulogic; + begin + reset_controller: entity work.soc_reset + generic map( + RESET_LOW => RESET_LOW + ) + port map( + ext_clk => ext_clk, + pll_clk => system_clk, + pll_locked_in => system_clk_locked, + ext_rst_in => ext_rst_n, + pll_rst_out => pll_rst, + rst_out => soc_rst + ); + + clkgen: entity work.clock_generator + generic map( + CLK_INPUT_HZ => 50000000, + CLK_OUTPUT_HZ => CLK_FREQUENCY + ) + port map( + ext_clk => ext_clk, + pll_rst_in => pll_rst, + pll_clk_out => system_clk, + pll_locked_out => system_clk_locked + ); + + core_alt_reset <= '0'; + + -- Vivado barfs on those differential signals if left + -- unconnected. So instanciate a diff. buffer and feed + -- it a constant '0'. + dummy_dram_clk: OBUFDS + port map ( + O => ddram_clk_p, + OB => ddram_clk_n, + I => ddram_clk_dummy + ); + ddram_clk_dummy <= '0'; + + end generate; + + has_dram: if USE_LITEDRAM generate + signal dram_init_done : std_ulogic; + signal dram_init_error : std_ulogic; + signal dram_sys_rst : std_ulogic; + signal rst_gen_rst : std_ulogic; + begin + + -- Eventually dig out the frequency from the generator + -- but for now, assert it's 100Mhz + assert CLK_FREQUENCY = 100000000; + + reset_controller: entity work.soc_reset + generic map( + RESET_LOW => RESET_LOW, + PLL_RESET_BITS => 18, + SOC_RESET_BITS => 1 + ) + port map( + ext_clk => ext_clk, + pll_clk => system_clk, + pll_locked_in => system_clk_locked, + ext_rst_in => ext_rst_n, + pll_rst_out => pll_rst, + rst_out => rst_gen_rst + ); + + -- Generate SoC reset + soc_rst_gen: process(system_clk) + begin + if ext_rst_n = '0' then + soc_rst <= '1'; + elsif rising_edge(system_clk) then + soc_rst <= dram_sys_rst or not system_clk_locked; + end if; + end process; + + dram: entity work.litedram_wrapper + generic map( + DRAM_ABITS => 24, + DRAM_ALINES => 14, + DRAM_DLINES => 16, + DRAM_PORT_WIDTH => 128, + PAYLOAD_FILE => RAM_INIT_FILE, + PAYLOAD_SIZE => PAYLOAD_SIZE + ) + port map( + clk_in => ext_clk, + rst => pll_rst, + system_clk => system_clk, + system_reset => dram_sys_rst, + core_alt_reset => core_alt_reset, + pll_locked => system_clk_locked, + + wb_in => wb_dram_in, + wb_out => wb_dram_out, + wb_ctrl_in => wb_ext_io_in, + wb_ctrl_out => wb_dram_ctrl_out, + wb_ctrl_is_csr => wb_ext_is_dram_csr, + wb_ctrl_is_init => wb_ext_is_dram_init, + + init_done => dram_init_done, + init_error => dram_init_error, + + ddram_a => ddram_a, + ddram_ba => ddram_ba, + ddram_ras_n => ddram_ras_n, + ddram_cas_n => ddram_cas_n, + ddram_we_n => ddram_we_n, + ddram_cs_n => open, + ddram_dm => ddram_dm, + ddram_dq => ddram_dq, + ddram_dqs_p => ddram_dqs_p, + ddram_dqs_n => ddram_dqs_n, + ddram_clk_p => ddram_clk_p, + ddram_clk_n => ddram_clk_n, + ddram_cke => ddram_cke, + ddram_odt => ddram_odt, + ddram_reset_n => ddram_reset_n + ); + + end generate; + + has_liteeth : if USE_LITEETH generate + + component liteeth_core port ( + sys_clock : in std_ulogic; + sys_reset : in std_ulogic; + gmii_eth_clocks_tx : in std_ulogic; + gmii_eth_clocks_gtx : out std_ulogic; + gmii_eth_clocks_rx : in std_ulogic; + gmii_eth_rst_n : out std_ulogic; + gmii_eth_mdio : inout std_ulogic; + gmii_eth_mdc : out std_ulogic; + gmii_eth_rx_dv : in std_ulogic; + gmii_eth_rx_er : in std_ulogic; + gmii_eth_rx_data : in std_ulogic_vector(7 downto 0); + gmii_eth_tx_en : out std_ulogic; + gmii_eth_tx_er : out std_ulogic; + gmii_eth_tx_data : out std_ulogic_vector(7 downto 0); + gmii_eth_col : in std_ulogic; + gmii_eth_crs : in std_ulogic; + wishbone_adr : in std_ulogic_vector(29 downto 0); + wishbone_dat_w : in std_ulogic_vector(31 downto 0); + wishbone_dat_r : out std_ulogic_vector(31 downto 0); + wishbone_sel : in std_ulogic_vector(3 downto 0); + wishbone_cyc : in std_ulogic; + wishbone_stb : in std_ulogic; + wishbone_ack : out std_ulogic; + wishbone_we : in std_ulogic; + wishbone_cti : in std_ulogic_vector(2 downto 0); + wishbone_bte : in std_ulogic_vector(1 downto 0); + wishbone_err : out std_ulogic; + interrupt : out std_ulogic + ); + end component; + + signal wb_eth_cyc : std_ulogic; + signal wb_eth_adr : std_ulogic_vector(29 downto 0); + + -- Change this to use a PLL instead of a BUFR to generate the 25Mhz + -- reference clock to the PHY. + constant USE_PLL : boolean := false; + begin + liteeth : liteeth_core + port map( + sys_clock => system_clk, + sys_reset => soc_rst, + gmii_eth_clocks_tx => eth_clocks_tx, + gmii_eth_clocks_gtx => eth_clocks_gtx, + gmii_eth_clocks_rx => eth_clocks_rx, + gmii_eth_rst_n => eth_rst_n, + gmii_eth_mdio => eth_mdio, + gmii_eth_mdc => eth_mdc, + gmii_eth_rx_dv => eth_rx_dv, + gmii_eth_rx_er => eth_rx_er, + gmii_eth_rx_data => eth_rx_data, + gmii_eth_tx_en => eth_tx_en, + gmii_eth_tx_er => eth_tx_er, + gmii_eth_tx_data => eth_tx_data, + gmii_eth_col => eth_col, + gmii_eth_crs => eth_crs, + wishbone_adr => wb_eth_adr, + wishbone_dat_w => wb_ext_io_in.dat, + wishbone_dat_r => wb_eth_out.dat, + wishbone_sel => wb_ext_io_in.sel, + wishbone_cyc => wb_eth_cyc, + wishbone_stb => wb_ext_io_in.stb, + wishbone_ack => wb_eth_out.ack, + wishbone_we => wb_ext_io_in.we, + wishbone_cti => "000", + wishbone_bte => "00", + wishbone_err => open, + interrupt => ext_irq_eth + ); + + -- Gate cyc with "chip select" from soc + wb_eth_cyc <= wb_ext_io_in.cyc and wb_ext_is_eth; + + -- Remove top address bits as liteeth decoder doesn't know about them + wb_eth_adr <= x"000" & "000" & wb_ext_io_in.adr(14 downto 0); + + -- LiteETH isn't pipelined + wb_eth_out.stall <= not wb_eth_out.ack; + + end generate; + + no_liteeth : if not USE_LITEETH generate + ext_irq_eth <= '0'; + end generate; + + -- SD card pmod + has_sdcard : if USE_LITESDCARD generate + component litesdcard_core port ( + clk : in std_ulogic; + rst : in std_ulogic; + -- wishbone for accessing control registers + wb_ctrl_adr : in std_ulogic_vector(29 downto 0); + wb_ctrl_dat_w : in std_ulogic_vector(31 downto 0); + wb_ctrl_dat_r : out std_ulogic_vector(31 downto 0); + wb_ctrl_sel : in std_ulogic_vector(3 downto 0); + wb_ctrl_cyc : in std_ulogic; + wb_ctrl_stb : in std_ulogic; + wb_ctrl_ack : out std_ulogic; + wb_ctrl_we : in std_ulogic; + wb_ctrl_cti : in std_ulogic_vector(2 downto 0); + wb_ctrl_bte : in std_ulogic_vector(1 downto 0); + wb_ctrl_err : out std_ulogic; + -- wishbone for SD card core to use for DMA + wb_dma_adr : out std_ulogic_vector(29 downto 0); + wb_dma_dat_w : out std_ulogic_vector(31 downto 0); + wb_dma_dat_r : in std_ulogic_vector(31 downto 0); + wb_dma_sel : out std_ulogic_vector(3 downto 0); + wb_dma_cyc : out std_ulogic; + wb_dma_stb : out std_ulogic; + wb_dma_ack : in std_ulogic; + wb_dma_we : out std_ulogic; + wb_dma_cti : out std_ulogic_vector(2 downto 0); + wb_dma_bte : out std_ulogic_vector(1 downto 0); + wb_dma_err : in std_ulogic; + -- connections to SD card + sdcard_data : inout std_ulogic_vector(3 downto 0); + sdcard_cmd : inout std_ulogic; + sdcard_clk : out std_ulogic; + sdcard_cd : in std_ulogic; + irq : out std_ulogic + ); + end component; + + signal wb_sdcard_cyc : std_ulogic; + signal wb_sdcard_adr : std_ulogic_vector(29 downto 0); + + begin + litesdcard : litesdcard_core + port map ( + clk => system_clk, + rst => soc_rst, + wb_ctrl_adr => wb_sdcard_adr, + wb_ctrl_dat_w => wb_ext_io_in.dat, + wb_ctrl_dat_r => wb_sdcard_out.dat, + wb_ctrl_sel => wb_ext_io_in.sel, + wb_ctrl_cyc => wb_sdcard_cyc, + wb_ctrl_stb => wb_ext_io_in.stb, + wb_ctrl_ack => wb_sdcard_out.ack, + wb_ctrl_we => wb_ext_io_in.we, + wb_ctrl_cti => "000", + wb_ctrl_bte => "00", + wb_ctrl_err => open, + wb_dma_adr => wb_sddma_nr.adr, + wb_dma_dat_w => wb_sddma_nr.dat, + wb_dma_dat_r => wb_sddma_ir.dat, + wb_dma_sel => wb_sddma_nr.sel, + wb_dma_cyc => wb_sddma_nr.cyc, + wb_dma_stb => wb_sddma_nr.stb, + wb_dma_ack => wb_sddma_ir.ack, + wb_dma_we => wb_sddma_nr.we, + wb_dma_cti => open, + wb_dma_bte => open, + wb_dma_err => '0', + sdcard_data => sdcard_data, + sdcard_cmd => sdcard_cmd, + sdcard_clk => sdcard_clk, + sdcard_cd => sdcard_cd, + irq => ext_irq_sdcard + ); + + -- Gate cyc with chip select from SoC + wb_sdcard_cyc <= wb_ext_io_in.cyc and wb_ext_is_sdcard; + + wb_sdcard_adr <= x"0000" & wb_ext_io_in.adr(13 downto 0); + + wb_sdcard_out.stall <= not wb_sdcard_out.ack; + + -- Convert non-pipelined DMA wishbone to pipelined by suppressing + -- non-acknowledged strobes + process(system_clk) + begin + if rising_edge(system_clk) then + wb_sddma_out <= wb_sddma_nr; + if wb_sddma_stb_sent = '1' or + (wb_sddma_out.stb = '1' and wb_sddma_in.stall = '0') then + wb_sddma_out.stb <= '0'; + end if; + if wb_sddma_nr.cyc = '0' or wb_sddma_ir.ack = '1' then + wb_sddma_stb_sent <= '0'; + elsif wb_sddma_in.stall = '0' then + wb_sddma_stb_sent <= wb_sddma_nr.stb; + end if; + wb_sddma_ir <= wb_sddma_in; + end if; + end process; + + end generate; + + -- Mux WB response on the IO bus + wb_ext_io_out <= wb_eth_out when wb_ext_is_eth = '1' else + wb_sdcard_out when wb_ext_is_sdcard = '1' else + wb_dram_ctrl_out; + + led0_n <= system_clk_locked; + led1_n <= not soc_rst; + +end architecture behaviour; diff --git a/fpga/wukong-v2.xdc b/fpga/wukong-v2.xdc new file mode 100644 index 0000000..def8f3e --- /dev/null +++ b/fpga/wukong-v2.xdc @@ -0,0 +1,487 @@ +################################################################################ +# clkin, reset, uart pins... +################################################################################ + +set_property -dict { PACKAGE_PIN M21 IOSTANDARD LVCMOS33 } [get_ports { ext_clk }]; + +set_property -dict { PACKAGE_PIN H7 IOSTANDARD LVCMOS33 } [get_ports { ext_rst_n }]; + +set_property -dict { PACKAGE_PIN E3 IOSTANDARD LVCMOS33 } [get_ports { uart_main_tx }]; +set_property -dict { PACKAGE_PIN F3 IOSTANDARD LVCMOS33 } [get_ports { uart_main_rx }]; + +################################################################################ +# LEDs +################################################################################ + +set_property -dict { PACKAGE_PIN V16 IOSTANDARD LVCMOS33 } [get_ports { led0_n }]; +set_property -dict { PACKAGE_PIN V17 IOSTANDARD LVCMOS33 } [get_ports { led1_n }]; + +################################################################################ +# SPI Flash +################################################################################ema + +set_property -dict { PACKAGE_PIN P18 IOSTANDARD LVCMOS33 } [get_ports { spi_flash_cs_n }]; +set_property -dict { PACKAGE_PIN R14 IOSTANDARD LVCMOS33 } [get_ports { spi_flash_mosi }]; +set_property -dict { PACKAGE_PIN R15 IOSTANDARD LVCMOS33 } [get_ports { spi_flash_miso }]; +set_property -dict { PACKAGE_PIN P14 IOSTANDARD LVCMOS33 } [get_ports { spi_flash_wp_n }]; +set_property -dict { PACKAGE_PIN N14 IOSTANDARD LVCMOS33 } [get_ports { spi_flash_hold_n }]; + +################################################################################ +# Micro SD +################################################################################ + +set_property -dict { PACKAGE_PIN M5 IOSTANDARD LVCMOS33 SLEW FAST } [get_ports { sdcard_data[0] }]; +set_property -dict { PACKAGE_PIN M7 IOSTANDARD LVCMOS33 SLEW FAST } [get_ports { sdcard_data[1] }]; +set_property -dict { PACKAGE_PIN H6 IOSTANDARD LVCMOS33 SLEW FAST } [get_ports { sdcard_data[2] }]; +set_property -dict { PACKAGE_PIN J6 IOSTANDARD LVCMOS33 SLEW FAST } [get_ports { sdcard_data[3] }]; +set_property -dict { PACKAGE_PIN J8 IOSTANDARD LVCMOS33 SLEW FAST } [get_ports { sdcard_cmd }]; +set_property -dict { PACKAGE_PIN L4 IOSTANDARD LVCMOS33 SLEW FAST } [get_ports { sdcard_clk }]; +set_property -dict { PACKAGE_PIN N6 IOSTANDARD LVCMOS33 } [get_ports { sdcard_cd }]; + +# Put registers into IOBs to improve timing +set_property IOB true [get_cells -hierarchical -filter {NAME =~*.litesdcard/sdcard_*}] + +################################################################################ +# PMOD header J10 (high-speed, no protection resisters) +################################################################################ + +#set_property -dict { PACKAGE_PIN D5 IOSTANDARD LVCMOS33 } [get_ports { pmod_j10_1 }]; +#set_property -dict { PACKAGE_PIN G5 IOSTANDARD LVCMOS33 } [get_ports { pmod_j10_2 }]; +#set_property -dict { PACKAGE_PIN G7 IOSTANDARD LVCMOS33 } [get_ports { pmod_j10_3 }]; +#set_property -dict { PACKAGE_PIN G8 IOSTANDARD LVCMOS33 } [get_ports { pmod_j10_4 }]; +#set_property -dict { PACKAGE_PIN E5 IOSTANDARD LVCMOS33 } [get_ports { pmod_j10_7 }]; +#set_property -dict { PACKAGE_PIN E6 IOSTANDARD LVCMOS33 } [get_ports { pmod_j10_8 }]; +#set_property -dict { PACKAGE_PIN D6 IOSTANDARD LVCMOS33 } [get_ports { pmod_j10_9 }]; +#set_property -dict { PACKAGE_PIN G6 IOSTANDARD LVCMOS33 } [get_ports { pmod_j10_10 }]; + +################################################################################ +# PMOD header J11 (high-speed, no protection resisters) +################################################################################ + +#set_property -dict { PACKAGE_PIN H4 IOSTANDARD LVCMOS33 } [get_ports { pmod_j11_1 }]; +#set_property -dict { PACKAGE_PIN F4 IOSTANDARD LVCMOS33 } [get_ports { pmod_j11_2 }]; +#set_property -dict { PACKAGE_PIN A4 IOSTANDARD LVCMOS33 } [get_ports { pmod_j11_3 }]; +#set_property -dict { PACKAGE_PIN A5 IOSTANDARD LVCMOS33 } [get_ports { pmod_j11_4 }]; +#set_property -dict { PACKAGE_PIN J4 IOSTANDARD LVCMOS33 } [get_ports { pmod_j11_7 }]; +#set_property -dict { PACKAGE_PIN G4 IOSTANDARD LVCMOS33 } [get_ports { pmod_j11_8 }]; +#set_property -dict { PACKAGE_PIN B4 IOSTANDARD LVCMOS33 } [get_ports { pmod_j11_9 }]; +#set_property -dict { PACKAGE_PIN B5 IOSTANDARD LVCMOS33 } [get_ports { pmod_j11_10 }]; + +################################################################################ +# HDR 20X2 connector +################################################################################ + +## TODO + +################################################################################ +# Ethernet (generated by LiteX) +################################################################################ + +# eth_clocks:0.tx +set_property LOC M2 [get_ports {eth_clocks_tx}] +set_property IOSTANDARD LVCMOS33 [get_ports {eth_clocks_tx}] + +# eth_clocks:0.gtx +set_property LOC U1 [get_ports {eth_clocks_gtx}] +set_property IOSTANDARD LVCMOS33 [get_ports {eth_clocks_gtx}] + +# eth_clocks:0.rx +set_property LOC P4 [get_ports {eth_clocks_rx}] +set_property IOSTANDARD LVCMOS33 [get_ports {eth_clocks_rx}] + +# eth:0.rst_n +set_property LOC R1 [get_ports {eth_rst_n}] +set_property IOSTANDARD LVCMOS33 [get_ports {eth_rst_n}] + +# eth:0.mdio +set_property LOC H1 [get_ports {eth_mdio}] +set_property IOSTANDARD LVCMOS33 [get_ports {eth_mdio}] + +# eth:0.mdc +set_property LOC H2 [get_ports {eth_mdc}] +set_property IOSTANDARD LVCMOS33 [get_ports {eth_mdc}] + +# eth:0.rx_dv +set_property LOC L3 [get_ports {eth_rx_dv}] +set_property IOSTANDARD LVCMOS33 [get_ports {eth_rx_dv}] + +# eth:0.rx_er +set_property LOC U5 [get_ports {eth_rx_er}] +set_property IOSTANDARD LVCMOS33 [get_ports {eth_rx_er}] + +# eth:0.rx_data +set_property LOC M4 [get_ports {eth_rx_data[0]}] +set_property IOSTANDARD LVCMOS33 [get_ports {eth_rx_data[0]}] + +# eth:0.rx_data +set_property LOC N3 [get_ports {eth_rx_data[1]}] +set_property IOSTANDARD LVCMOS33 [get_ports {eth_rx_data[1]}] + +# eth:0.rx_data +set_property LOC N4 [get_ports {eth_rx_data[2]}] +set_property IOSTANDARD LVCMOS33 [get_ports {eth_rx_data[2]}] + +# eth:0.rx_data +set_property LOC P3 [get_ports {eth_rx_data[3]}] +set_property IOSTANDARD LVCMOS33 [get_ports {eth_rx_data[3]}] + +# eth:0.rx_data +set_property LOC R3 [get_ports {eth_rx_data[4]}] +set_property IOSTANDARD LVCMOS33 [get_ports {eth_rx_data[4]}] + +# eth:0.rx_data +set_property LOC T3 [get_ports {eth_rx_data[5]}] +set_property IOSTANDARD LVCMOS33 [get_ports {eth_rx_data[5]}] + +# eth:0.rx_data +set_property LOC T4 [get_ports {eth_rx_data[6]}] +set_property IOSTANDARD LVCMOS33 [get_ports {eth_rx_data[6]}] + +# eth:0.rx_data +set_property LOC T5 [get_ports {eth_rx_data[7]}] +set_property IOSTANDARD LVCMOS33 [get_ports {eth_rx_data[7]}] + +# eth:0.tx_en +set_property LOC T2 [get_ports {eth_tx_en}] +set_property IOSTANDARD LVCMOS33 [get_ports {eth_tx_en}] + +# eth:0.tx_er +set_property LOC J1 [get_ports {eth_tx_er}] +set_property IOSTANDARD LVCMOS33 [get_ports {eth_tx_er}] + +# eth:0.tx_data +set_property LOC R2 [get_ports {eth_tx_data[0]}] +set_property IOSTANDARD LVCMOS33 [get_ports {eth_tx_data[0]}] + +# eth:0.tx_data +set_property LOC P1 [get_ports {eth_tx_data[1]}] +set_property IOSTANDARD LVCMOS33 [get_ports {eth_tx_data[1]}] + +# eth:0.tx_data +set_property LOC N2 [get_ports {eth_tx_data[2]}] +set_property IOSTANDARD LVCMOS33 [get_ports {eth_tx_data[2]}] + +# eth:0.tx_data +set_property LOC N1 [get_ports {eth_tx_data[3]}] +set_property IOSTANDARD LVCMOS33 [get_ports {eth_tx_data[3]}] + +# eth:0.tx_data +set_property LOC M1 [get_ports {eth_tx_data[4]}] +set_property IOSTANDARD LVCMOS33 [get_ports {eth_tx_data[4]}] + +# eth:0.tx_data +set_property LOC L2 [get_ports {eth_tx_data[5]}] +set_property IOSTANDARD LVCMOS33 [get_ports {eth_tx_data[5]}] + +# eth:0.tx_data +set_property LOC K2 [get_ports {eth_tx_data[6]}] +set_property IOSTANDARD LVCMOS33 [get_ports {eth_tx_data[6]}] + +# eth:0.tx_data +set_property LOC K1 [get_ports {eth_tx_data[7]}] +set_property IOSTANDARD LVCMOS33 [get_ports {eth_tx_data[7]}] + +# eth:0.col +set_property LOC U4 [get_ports {eth_col}] +set_property IOSTANDARD LVCMOS33 [get_ports {eth_col}] + +# eth:0.crs +set_property LOC U2 [get_ports {eth_crs}] +set_property IOSTANDARD LVCMOS33 [get_ports {eth_crs}] + +################################################################################ +# DRAM (generated by LiteX) +################################################################################ + +# ddram:0.a +set_property LOC E17 [get_ports {ddram_a[0]}] +set_property SLEW FAST [get_ports {ddram_a[0]}] +set_property IOSTANDARD SSTL135 [get_ports {ddram_a[0]}] + +# ddram:0.a +set_property LOC G17 [get_ports {ddram_a[1]}] +set_property SLEW FAST [get_ports {ddram_a[1]}] +set_property IOSTANDARD SSTL135 [get_ports {ddram_a[1]}] + +# ddram:0.a +set_property LOC F17 [get_ports {ddram_a[2]}] +set_property SLEW FAST [get_ports {ddram_a[2]}] +set_property IOSTANDARD SSTL135 [get_ports {ddram_a[2]}] + +# ddram:0.a +set_property LOC C17 [get_ports {ddram_a[3]}] +set_property SLEW FAST [get_ports {ddram_a[3]}] +set_property IOSTANDARD SSTL135 [get_ports {ddram_a[3]}] + +# ddram:0.a +set_property LOC G16 [get_ports {ddram_a[4]}] +set_property SLEW FAST [get_ports {ddram_a[4]}] +set_property IOSTANDARD SSTL135 [get_ports {ddram_a[4]}] + +# ddram:0.a +set_property LOC D16 [get_ports {ddram_a[5]}] +set_property SLEW FAST [get_ports {ddram_a[5]}] +set_property IOSTANDARD SSTL135 [get_ports {ddram_a[5]}] + +# ddram:0.a +set_property LOC H16 [get_ports {ddram_a[6]}] +set_property SLEW FAST [get_ports {ddram_a[6]}] +set_property IOSTANDARD SSTL135 [get_ports {ddram_a[6]}] + +# ddram:0.a +set_property LOC E16 [get_ports {ddram_a[7]}] +set_property SLEW FAST [get_ports {ddram_a[7]}] +set_property IOSTANDARD SSTL135 [get_ports {ddram_a[7]}] + +# ddram:0.a +set_property LOC H14 [get_ports {ddram_a[8]}] +set_property SLEW FAST [get_ports {ddram_a[8]}] +set_property IOSTANDARD SSTL135 [get_ports {ddram_a[8]}] + +# ddram:0.a +set_property LOC F15 [get_ports {ddram_a[9]}] +set_property SLEW FAST [get_ports {ddram_a[9]}] +set_property IOSTANDARD SSTL135 [get_ports {ddram_a[9]}] + +# ddram:0.a +set_property LOC F20 [get_ports {ddram_a[10]}] +set_property SLEW FAST [get_ports {ddram_a[10]}] +set_property IOSTANDARD SSTL135 [get_ports {ddram_a[10]}] + +# ddram:0.a +set_property LOC H15 [get_ports {ddram_a[11]}] +set_property SLEW FAST [get_ports {ddram_a[11]}] +set_property IOSTANDARD SSTL135 [get_ports {ddram_a[11]}] + +# ddram:0.a +set_property LOC C18 [get_ports {ddram_a[12]}] +set_property SLEW FAST [get_ports {ddram_a[12]}] +set_property IOSTANDARD SSTL135 [get_ports {ddram_a[12]}] + +# ddram:0.a +set_property LOC G15 [get_ports {ddram_a[13]}] +set_property SLEW FAST [get_ports {ddram_a[13]}] +set_property IOSTANDARD SSTL135 [get_ports {ddram_a[13]}] + +# ddram:0.ba +set_property LOC B17 [get_ports {ddram_ba[0]}] +set_property SLEW FAST [get_ports {ddram_ba[0]}] +set_property IOSTANDARD SSTL135 [get_ports {ddram_ba[0]}] + +# ddram:0.ba +set_property LOC D18 [get_ports {ddram_ba[1]}] +set_property SLEW FAST [get_ports {ddram_ba[1]}] +set_property IOSTANDARD SSTL135 [get_ports {ddram_ba[1]}] + +# ddram:0.ba +set_property LOC A17 [get_ports {ddram_ba[2]}] +set_property SLEW FAST [get_ports {ddram_ba[2]}] +set_property IOSTANDARD SSTL135 [get_ports {ddram_ba[2]}] + +# ddram:0.ras_n +set_property LOC A19 [get_ports {ddram_ras_n}] +set_property SLEW FAST [get_ports {ddram_ras_n}] +set_property IOSTANDARD SSTL135 [get_ports {ddram_ras_n}] + +# ddram:0.cas_n +set_property LOC B19 [get_ports {ddram_cas_n}] +set_property SLEW FAST [get_ports {ddram_cas_n}] +set_property IOSTANDARD SSTL135 [get_ports {ddram_cas_n}] + +# ddram:0.we_n +set_property LOC A18 [get_ports {ddram_we_n}] +set_property SLEW FAST [get_ports {ddram_we_n}] +set_property IOSTANDARD SSTL135 [get_ports {ddram_we_n}] + +# ddram:0.dm +set_property LOC A22 [get_ports {ddram_dm[0]}] +set_property SLEW FAST [get_ports {ddram_dm[0]}] +set_property IOSTANDARD SSTL135 [get_ports {ddram_dm[0]}] + +# ddram:0.dm +set_property LOC C22 [get_ports {ddram_dm[1]}] +set_property SLEW FAST [get_ports {ddram_dm[1]}] +set_property IOSTANDARD SSTL135 [get_ports {ddram_dm[1]}] + +# ddram:0.dq +set_property LOC D21 [get_ports {ddram_dq[0]}] +set_property SLEW FAST [get_ports {ddram_dq[0]}] +set_property IOSTANDARD SSTL135 [get_ports {ddram_dq[0]}] +set_property IN_TERM UNTUNED_SPLIT_40 [get_ports {ddram_dq[0]}] + +# ddram:0.dq +set_property LOC C21 [get_ports {ddram_dq[1]}] +set_property SLEW FAST [get_ports {ddram_dq[1]}] +set_property IOSTANDARD SSTL135 [get_ports {ddram_dq[1]}] +set_property IN_TERM UNTUNED_SPLIT_40 [get_ports {ddram_dq[1]}] + +# ddram:0.dq +set_property LOC B22 [get_ports {ddram_dq[2]}] +set_property SLEW FAST [get_ports {ddram_dq[2]}] +set_property IOSTANDARD SSTL135 [get_ports {ddram_dq[2]}] +set_property IN_TERM UNTUNED_SPLIT_40 [get_ports {ddram_dq[2]}] + +# ddram:0.dq +set_property LOC B21 [get_ports {ddram_dq[3]}] +set_property SLEW FAST [get_ports {ddram_dq[3]}] +set_property IOSTANDARD SSTL135 [get_ports {ddram_dq[3]}] +set_property IN_TERM UNTUNED_SPLIT_40 [get_ports {ddram_dq[3]}] + +# ddram:0.dq +set_property LOC D19 [get_ports {ddram_dq[4]}] +set_property SLEW FAST [get_ports {ddram_dq[4]}] +set_property IOSTANDARD SSTL135 [get_ports {ddram_dq[4]}] +set_property IN_TERM UNTUNED_SPLIT_40 [get_ports {ddram_dq[4]}] + +# ddram:0.dq +set_property LOC E20 [get_ports {ddram_dq[5]}] +set_property SLEW FAST [get_ports {ddram_dq[5]}] +set_property IOSTANDARD SSTL135 [get_ports {ddram_dq[5]}] +set_property IN_TERM UNTUNED_SPLIT_40 [get_ports {ddram_dq[5]}] + +# ddram:0.dq +set_property LOC C19 [get_ports {ddram_dq[6]}] +set_property SLEW FAST [get_ports {ddram_dq[6]}] +set_property IOSTANDARD SSTL135 [get_ports {ddram_dq[6]}] +set_property IN_TERM UNTUNED_SPLIT_40 [get_ports {ddram_dq[6]}] + +# ddram:0.dq +set_property LOC D20 [get_ports {ddram_dq[7]}] +set_property SLEW FAST [get_ports {ddram_dq[7]}] +set_property IOSTANDARD SSTL135 [get_ports {ddram_dq[7]}] +set_property IN_TERM UNTUNED_SPLIT_40 [get_ports {ddram_dq[7]}] + +# ddram:0.dq +set_property LOC C23 [get_ports {ddram_dq[8]}] +set_property SLEW FAST [get_ports {ddram_dq[8]}] +set_property IOSTANDARD SSTL135 [get_ports {ddram_dq[8]}] +set_property IN_TERM UNTUNED_SPLIT_40 [get_ports {ddram_dq[8]}] + +# ddram:0.dq +set_property LOC D23 [get_ports {ddram_dq[9]}] +set_property SLEW FAST [get_ports {ddram_dq[9]}] +set_property IOSTANDARD SSTL135 [get_ports {ddram_dq[9]}] +set_property IN_TERM UNTUNED_SPLIT_40 [get_ports {ddram_dq[9]}] + +# ddram:0.dq +set_property LOC B24 [get_ports {ddram_dq[10]}] +set_property SLEW FAST [get_ports {ddram_dq[10]}] +set_property IOSTANDARD SSTL135 [get_ports {ddram_dq[10]}] +set_property IN_TERM UNTUNED_SPLIT_40 [get_ports {ddram_dq[10]}] + +# ddram:0.dq +set_property LOC B25 [get_ports {ddram_dq[11]}] +set_property SLEW FAST [get_ports {ddram_dq[11]}] +set_property IOSTANDARD SSTL135 [get_ports {ddram_dq[11]}] +set_property IN_TERM UNTUNED_SPLIT_40 [get_ports {ddram_dq[11]}] + +# ddram:0.dq +set_property LOC C24 [get_ports {ddram_dq[12]}] +set_property SLEW FAST [get_ports {ddram_dq[12]}] +set_property IOSTANDARD SSTL135 [get_ports {ddram_dq[12]}] +set_property IN_TERM UNTUNED_SPLIT_40 [get_ports {ddram_dq[12]}] + +# ddram:0.dq +set_property LOC C26 [get_ports {ddram_dq[13]}] +set_property SLEW FAST [get_ports {ddram_dq[13]}] +set_property IOSTANDARD SSTL135 [get_ports {ddram_dq[13]}] +set_property IN_TERM UNTUNED_SPLIT_40 [get_ports {ddram_dq[13]}] + +# ddram:0.dq +set_property LOC A25 [get_ports {ddram_dq[14]}] +set_property SLEW FAST [get_ports {ddram_dq[14]}] +set_property IOSTANDARD SSTL135 [get_ports {ddram_dq[14]}] +set_property IN_TERM UNTUNED_SPLIT_40 [get_ports {ddram_dq[14]}] + +# ddram:0.dq +set_property LOC B26 [get_ports {ddram_dq[15]}] +set_property SLEW FAST [get_ports {ddram_dq[15]}] +set_property IOSTANDARD SSTL135 [get_ports {ddram_dq[15]}] +set_property IN_TERM UNTUNED_SPLIT_40 [get_ports {ddram_dq[15]}] + +# ddram:0.dqs_p +set_property LOC B20 [get_ports {ddram_dqs_p[0]}] +set_property SLEW FAST [get_ports {ddram_dqs_p[0]}] +set_property IOSTANDARD DIFF_SSTL135 [get_ports {ddram_dqs_p[0]}] +set_property IN_TERM UNTUNED_SPLIT_40 [get_ports {ddram_dqs_p[0]}] + +# ddram:0.dqs_p +set_property LOC A23 [get_ports {ddram_dqs_p[1]}] +set_property SLEW FAST [get_ports {ddram_dqs_p[1]}] +set_property IOSTANDARD DIFF_SSTL135 [get_ports {ddram_dqs_p[1]}] +set_property IN_TERM UNTUNED_SPLIT_40 [get_ports {ddram_dqs_p[1]}] + +# ddram:0.dqs_n +set_property LOC A20 [get_ports {ddram_dqs_n[0]}] +set_property SLEW FAST [get_ports {ddram_dqs_n[0]}] +set_property IOSTANDARD DIFF_SSTL135 [get_ports {ddram_dqs_n[0]}] +set_property IN_TERM UNTUNED_SPLIT_40 [get_ports {ddram_dqs_n[0]}] + +# ddram:0.dqs_n +set_property LOC A24 [get_ports {ddram_dqs_n[1]}] +set_property SLEW FAST [get_ports {ddram_dqs_n[1]}] +set_property IOSTANDARD DIFF_SSTL135 [get_ports {ddram_dqs_n[1]}] +set_property IN_TERM UNTUNED_SPLIT_40 [get_ports {ddram_dqs_n[1]}] + +# ddram:0.clk_p +set_property LOC F18 [get_ports {ddram_clk_p}] +set_property SLEW FAST [get_ports {ddram_clk_p}] +set_property IOSTANDARD DIFF_SSTL135 [get_ports {ddram_clk_p}] + +# ddram:0.clk_n +set_property LOC F19 [get_ports {ddram_clk_n}] +set_property SLEW FAST [get_ports {ddram_clk_n}] +set_property IOSTANDARD DIFF_SSTL135 [get_ports {ddram_clk_n}] + +# ddram:0.cke +set_property LOC E18 [get_ports {ddram_cke}] +set_property SLEW FAST [get_ports {ddram_cke}] +set_property IOSTANDARD SSTL135 [get_ports {ddram_cke}] + +# ddram:0.odt +set_property LOC G19 [get_ports {ddram_odt}] +set_property SLEW FAST [get_ports {ddram_odt}] +set_property IOSTANDARD SSTL135 [get_ports {ddram_odt}] + +# ddram:0.reset_n +set_property LOC H17 [get_ports {ddram_reset_n}] +set_property SLEW FAST [get_ports {ddram_reset_n}] +set_property IOSTANDARD SSTL135 [get_ports {ddram_reset_n}] + +################################################################################ +# Design constraints and bitsteam attributes +################################################################################ + +set_property INTERNAL_VREF 0.675 [get_iobanks 16] + +set_property CONFIG_VOLTAGE 3.3 [current_design] +set_property CFGBVS VCCO [current_design] + +set_property BITSTREAM.GENERAL.COMPRESS TRUE [current_design] +set_property BITSTREAM.CONFIG.CONFIGRATE 33 [current_design] +set_property CONFIG_MODE SPIx4 [current_design] + +################################################################################ +# Clock constraints +################################################################################ + +create_clock -name sys_clk_pin -period 20.00 [get_ports { ext_clk }]; + +create_clock -name eth_rx_clk -period 8.0 [get_nets has_liteeth.liteeth/eth_rx_clk] +create_clock -name eth_tx_clk -period 8.0 [get_nets has_liteeth.liteeth/eth_tx_clk] + +set_clock_groups -group [get_clocks -include_generated_clocks -of [get_nets has_liteeth.liteeth/sys_clk]] -group [get_clocks -include_generated_clocks -of [get_nets has_liteeth.liteeth/eth_rx_clk]] -asynchronous + +set_clock_groups -group [get_clocks -include_generated_clocks -of [get_nets has_liteeth.liteeth/sys_clk]] -group [get_clocks -include_generated_clocks -of [get_nets has_liteeth.liteeth/eth_tx_clk]] -asynchronous + +set_clock_groups -group [get_clocks -include_generated_clocks -of [get_nets has_liteeth.liteeth/eth_rx_clk]] -group [get_clocks -include_generated_clocks -of [get_nets has_liteeth.liteeth/eth_tx_clk]] -asynchronous + +################################################################################ +# False path constraints (from LiteX as they relate to LiteDRAM and LiteEth) +################################################################################ + +set_false_path -quiet -through [get_nets -hierarchical -filter {mr_ff == TRUE}] + +set_false_path -quiet -to [get_pins -filter {REF_PIN_NAME == PRE} -of_objects [get_cells -hierarchical -filter {ars_ff1 == TRUE || ars_ff2 == TRUE}]] + +set_max_delay 2 -quiet -from [get_pins -filter {REF_PIN_NAME == C} -of_objects [get_cells -hierarchical -filter {ars_ff1 == TRUE}]] -to [get_pins -filter {REF_PIN_NAME == D} -of_objects [get_cells -hierarchical -filter {ars_ff2 == TRUE}]] diff --git a/litedram/gen-src/generate.py b/litedram/gen-src/generate.py index a6018c6..2808f2a 100755 --- a/litedram/gen-src/generate.py +++ b/litedram/gen-src/generate.py @@ -100,7 +100,7 @@ def generate_one(t): def main(): - targets = ['arty','nexys-video', 'genesys2', 'acorn-cle-215', 'sim'] + targets = ['arty','nexys-video', 'genesys2', 'acorn-cle-215', 'wukong-v2', 'sim'] for t in targets: generate_one(t) diff --git a/litedram/gen-src/wukong-v2.yml b/litedram/gen-src/wukong-v2.yml new file mode 100644 index 0000000..814b906 --- /dev/null +++ b/litedram/gen-src/wukong-v2.yml @@ -0,0 +1,36 @@ +# This file is Copyright (c) 2018-2019 Florent Kermarrec +# License: BSD + +{ + # General ------------------------------------------------------------------ + "cpu": "None", # CPU type (ex vexriscv, serv, None) + "speedgrade": -1, # FPGA speedgrade + "memtype": "DDR3", # DRAM type + + # PHY ---------------------------------------------------------------------- + "cmd_latency": 0, # Command additional latency + "sdram_module": "MT41K128M16", # SDRAM modules of the board or SO-DIMM + "sdram_module_nb": 2, # Number of byte groups + "sdram_rank_nb": 1, # Number of ranks + "sdram_phy": "A7DDRPHY", # Type of FPGA PHY + + # Electrical --------------------------------------------------------------- + "rtt_nom": "60ohm", # Nominal termination + "rtt_wr": "60ohm", # Write termination + "ron": "34ohm", # Output driver impedance + + # Frequency ---------------------------------------------------------------- + "input_clk_freq": 50e6, # Input clock frequency + "sys_clk_freq": 100e6, # System clock frequency (DDR_clk = 4 x sys_clk) + "iodelay_clk_freq": 200e6, # IODELAYs reference clock frequency + + # Core --------------------------------------------------------------------- + "cmd_buffer_depth": 16, # Depth of the command buffer + + # User Ports --------------------------------------------------------------- + "user_ports": { + "native_0": { + "type": "native", + }, + }, +} diff --git a/liteeth/gen-src/generate.sh b/liteeth/gen-src/generate.sh index ba1ba46..96203eb 100755 --- a/liteeth/gen-src/generate.sh +++ b/liteeth/gen-src/generate.sh @@ -1,6 +1,6 @@ #!/bin/bash -TARGETS="arty nexys-video" +TARGETS="arty nexys-video wukong-v2" ME=$(realpath $0) echo ME=$ME diff --git a/liteeth/gen-src/wukong-v2.yml b/liteeth/gen-src/wukong-v2.yml new file mode 100644 index 0000000..c8d43a0 --- /dev/null +++ b/liteeth/gen-src/wukong-v2.yml @@ -0,0 +1,17 @@ +# This file is Copyright (c) 2020 Florent Kermarrec +# License: BSD + +# PHY ---------------------------------------------------------------------- +phy: LiteEthPHYGMIIMII +vendor: xilinx +device: xc7 +# Core --------------------------------------------------------------------- +clk_freq: 100e6 +core: wishbone +endianness: little +ntxslots: 2 +nrxslots: 2 + +soc: + mem_map: + ethmac: 0x00010000 diff --git a/microwatt.core b/microwatt.core index 8443911..f463d90 100644 --- a/microwatt.core +++ b/microwatt.core @@ -106,6 +106,12 @@ filesets: - fpga/clk_gen_plle2.vhd : {file_type : vhdlSource-2008} - fpga/top-arty.vhdl : {file_type : vhdlSource-2008} + wukong-v2: + files: + - fpga/wukong-v2.xdc : {file_type : xdc} + - fpga/clk_gen_plle2.vhd : {file_type : vhdlSource-2008} + - fpga/top-wukong-v2.vhdl : {file_type : vhdlSource-2008} + cmod_a7-35: files: - fpga/cmod_a7-35.xdc : {file_type : xdc} @@ -338,6 +344,50 @@ targets: vivado: {part : xc7a100ticsg324-1L} toplevel : toplevel + wukong-v2-a100t-nodram: + default_tool: vivado + filesets: [core, wukong-v2, soc, fpga, debug_xilinx, uart16550, xilinx_specific, litesdcard] + parameters: + - memory_size + - ram_init_file + - use_litedram=false + - use_liteeth=false + - use_litesdcard=true + - disable_flatten_core + - spi_flash_offset=4194304 + - clk_frequency=100000000 + - log_length=2048 + - uart_is_16550 + - has_fpu + - has_btc + - has_short_mult + generate: [litesdcard_wukong-v2] + tools: + vivado: {part : xc7a100tfgg676-1} + toplevel : toplevel + + wukong-v2-a100t: + default_tool: vivado + filesets: [core, wukong-v2, soc, fpga, debug_xilinx, litedram, liteeth, uart16550, xilinx_specific, litesdcard] + parameters: + - memory_size=0 + - ram_init_file + - use_litedram=true + - use_liteeth=true + - use_litesdcard=true + - disable_flatten_core + - no_bram=true + - spi_flash_offset=4194304 + - log_length=0 + - uart_is_16550 + - has_fpu + - has_btc + - has_short_mult + generate: [litedram_wukong-v2, liteeth_wukong-v2, litesdcard_wukong-v2] + tools: + vivado: {part : xc7a100tfgg676-1} + toplevel : toplevel + cmod_a7-35: default_tool: vivado filesets: [core, cmod_a7-35, soc, fpga, debug_xilinx, uart16550, xilinx_specific] @@ -395,6 +445,18 @@ generate: generator: litedram_gen parameters: {board : genesys2} + litedram_wukong-v2: + generator: litedram_gen + parameters: {board : wukong-v2} + + liteeth_wukong-v2: + generator: liteeth_gen + parameters: {board : wukong-v2} + + litesdcard_wukong-v2: + generator: litesdcard_gen + parameters: {vendor : xilinx} + parameters: memory_size: datatype : int