From: Eddie Hung <eddie@fpgeh.com>
Date: Wed, 22 Jan 2020 22:22:03 +0000 (-0800)
Subject: Fix $__ABC9_ASYNC1 to output 1'b1 not 1'b0
X-Git-Tag: working-ls180~849^2~10
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=da134701cd86e3958490b97fd6d840ce24586080;p=yosys.git

Fix $__ABC9_ASYNC1 to output 1'b1 not 1'b0
---

diff --git a/techlibs/xilinx/abc9_model.v b/techlibs/xilinx/abc9_model.v
index 204fa883f..15d12c89f 100644
--- a/techlibs/xilinx/abc9_model.v
+++ b/techlibs/xilinx/abc9_model.v
@@ -42,7 +42,7 @@ endmodule
 // Box to emulate async behaviour of FDP*
 (* abc9_box_id = 1001, lib_whitebox *)
 module \$__ABC9_ASYNC1 (input A, S, output Y);
-  assign Y = S ? 1'b0 : A;
+  assign Y = S ? 1'b1 : A;
 endmodule
 
 // Box to emulate comb/seq behaviour of RAM{32,64} and SRL{16,32}