From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Thu, 18 Jul 2019 16:39:07 +0000 (+0100)
Subject: update comments
X-Git-Tag: ls180-24jan2020~812
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=da2859105a4b40c346ebf4ac7ac2071edbc59ddf;p=ieee754fpu.git

update comments
---

diff --git a/src/ieee754/fcvt/pipeline.py b/src/ieee754/fcvt/pipeline.py
index 941d1aeb..3ba53148 100644
--- a/src/ieee754/fcvt/pipeline.py
+++ b/src/ieee754/fcvt/pipeline.py
@@ -93,6 +93,16 @@ class FPCVTIntToFloatMod(Elaboratable):
             m.d.comb += zo.m[ms:].eq(msb.m_out[3:])
         m.d.comb += zo.create(zo.s, zo.e, zo.m) # ... here
 
+        # note: post-normalisation actually appears to be capable of
+        # detecting overflow to infinity (FPPackMod).  so it's ok to
+        # drop the bits into the mantissa (with a fixed exponent),
+        # do some rounding (which might result in exceeding the
+        # range of the target FP by re-increasing the exponent),
+        # and basically *not* have to do any kind of range-checking
+        # here: just set up guard/round/sticky, drop the INT into the
+        # mantissa, and away we go.  XXX TODO: see if FPNormaliseMod
+        # is even necessary.  it probably isn't
+
         # initialise rounding (but only activate if needed)
         if ms < 0:
             # larger int to smaller FP (uint32/64 -> fp16 most likely)