From: Sebastien Bourdeauducq <sebastien@milkymist.org>
Date: Wed, 17 Jul 2013 11:54:05 +0000 (+0200)
Subject: cif: fix indentation
X-Git-Tag: 24jan2021_ls180~2859
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=da2b7aa961dc0c3dbf5a7f17a8669b273b70b69b;p=litex.git

cif: fix indentation
---

diff --git a/milkymist/cif.py b/milkymist/cif.py
index b9a85015..d040ccdd 100644
--- a/milkymist/cif.py
+++ b/milkymist/cif.py
@@ -67,30 +67,30 @@ def get_csr_header(csr_base, bank_array, interrupt_map):
 	return r
 
 def get_sdram_phy_header(sdram_phy):
-		if sdram_phy.phy_settings.type not in ["SDR", "DDR", "LPDDR", "DDR2"]:
-			raise NotImplementedError("The SDRAM PHY header generator only supports SDR, DDR, LPDDR and DDR2")
+	if sdram_phy.phy_settings.type not in ["SDR", "DDR", "LPDDR", "DDR2"]:
+		raise NotImplementedError("The SDRAM PHY header generator only supports SDR, DDR, LPDDR and DDR2")
 
-		r = "#ifndef __HW_SDRAM_PHY_H\n#define __HW_SDRAM_PHY_H\n"
-		r += "#include <hw/common.h>\n#include <hw/csr.h>\n#include <hw/flags.h>\n\n"
+	r = "#ifndef __HW_SDRAM_PHY_H\n#define __HW_SDRAM_PHY_H\n"
+	r += "#include <hw/common.h>\n#include <hw/csr.h>\n#include <hw/flags.h>\n\n"
 
-		r += "static void cdelay(int i);\n"
+	r += "static void cdelay(int i);\n"
 
-		#
-		# commands_px functions
-		# 
-		for n in range(sdram_phy.phy_settings.nphases):
-			r += """
+	#
+	# commands_px functions
+	# 
+	for n in range(sdram_phy.phy_settings.nphases):
+		r += """
 static void command_p{n}(int cmd)
 {{
 	dfii_pi{n}_command_write(cmd);
 	dfii_pi{n}_command_issue_write(1);
 }}""".format(n=str(n))
-		r += "\n\n"
+	r += "\n\n"
 
-		#
-		# rd/wr access macros
-		#
-		r += """
+	#
+	# rd/wr access macros
+	#
+	r += """
 #define dfii_pird_address_write(X) dfii_pi{rdphase}_address_write(X)
 #define dfii_piwr_address_write(X) dfii_pi{wrphase}_address_write(X)
 
@@ -100,105 +100,105 @@ static void command_p{n}(int cmd)
 #define command_prd(X) command_p{rdphase}(X)
 #define command_pwr(X) command_p{wrphase}(X)
 """.format(rdphase=str(sdram_phy.phy_settings.rdphase), wrphase=str(sdram_phy.phy_settings.wrphase)) 
-		r +="\n"
-		
-		#
-		# init sequence
-		# 
-		cmds = {
-			"PRECHARGE_ALL" : "DFII_COMMAND_RAS|DFII_COMMAND_WE|DFII_COMMAND_CS",
-			"MODE_REGISTER" : "DFII_COMMAND_RAS|DFII_COMMAND_CAS|DFII_COMMAND_WE|DFII_COMMAND_CS",
-			"AUTO_REFRESH"  : "DFII_COMMAND_RAS|DFII_COMMAND_CAS|DFII_COMMAND_CS",
-			"CKE"           : "DFII_CONTROL_CKE"
-		}
-
-		def gen_cmd(comment, a, ba, cmd, delay):	
-			r = "\t/* {0} */\n".format(comment)
-			r += "\tdfii_pi0_address_write({0:#x});\n".format(a)
-			r += "\tdfii_pi0_baddress_write({0:d});\n".format(ba)
-			if "CKE" in cmd:
-				r += "\tdfii_control_write({0});\n".format(cmd)
-			else:
-				r += "\tcommand_p0({0});\n".format(cmd)
-			r += "\tcdelay({0:d});\n".format(delay)
-			r += "\n"
-			return r
-
-
-		r += "static void init_sequence(void)\n{\n"
-
-		cl = sdram_phy.phy_settings.cl
-		
-		if sdram_phy.phy_settings.type == "SDR":
-			bl = 1*sdram_phy.phy_settings.nphases
-			mr  = log2_int(bl) + (cl << 4)
-			reset_dll = 1 << 8
-
-			init_sequence = [
-				("Bring CKE high", 0x0000, 0, cmds["CKE"], 2000),
-				("Precharge All",  0x0400, 0, cmds["PRECHARGE_ALL"], 0),
-				("Load Mode Register / Reset DLL, CL={0:d}, BL={1:d}".format(cl, bl), mr + reset_dll, 0, cmds["MODE_REGISTER"], 200),
-				("Precharge All", 0x0400, 0, cmds["PRECHARGE_ALL"], 0),
-				("Auto Refresh", 0x0, 0, cmds["AUTO_REFRESH"], 4),
-				("Auto Refresh", 0x0, 0, cmds["AUTO_REFRESH"], 4),
-				("Load Mode Register / CL={0:d}, BL={1:d}".format(cl, bl), mr, 0, cmds["MODE_REGISTER"], 200)
-			]
-
-		elif sdram_phy.phy_settings.type == "DDR":
-			bl = 2*sdram_phy.phy_settings.nphases
-			mr  = log2_int(bl) + (cl << 4)
-			emr = 0
-			reset_dll = 1 << 8
- 
-			init_sequence = [
-				("Bring CKE high", 0x0000, 0, cmds["CKE"], 2000),
-				("Precharge All",  0x0400, 0, cmds["PRECHARGE_ALL"], 0),
-				("Load Extended Mode Register", emr, 1, cmds["MODE_REGISTER"], 0),
-				("Load Mode Register / Reset DLL, CL={0:d}, BL={1:d}".format(cl, bl), mr + reset_dll, 0, cmds["MODE_REGISTER"], 200),
-				("Precharge All", 0x0400, 0, cmds["PRECHARGE_ALL"], 0),
-				("Auto Refresh", 0x0, 0, cmds["AUTO_REFRESH"], 4),
-				("Auto Refresh", 0x0, 0, cmds["AUTO_REFRESH"], 4),
-				("Load Mode Register / CL={0:d}, BL={1:d}".format(cl, bl), mr, 0, cmds["MODE_REGISTER"], 200)
-			]
-
-		elif sdram_phy.phy_settings.type == "LPDDR":
-			bl = 2*sdram_phy.phy_settings.nphases
-			mr  = log2_int(bl) + (cl << 4)
-			emr = 0
-			reset_dll = 1 << 8
-
-			init_sequence = [
-				("Bring CKE high", 0x0000, 0, cmds["CKE"], 2000),
-				("Precharge All",  0x0400, 0, cmds["PRECHARGE_ALL"], 0),
-				("Load Extended Mode Register", emr, 2, cmds["MODE_REGISTER"], 0),
-				("Load Mode Register / Reset DLL, CL={0:d}, BL={1:d}".format(cl, bl), mr + reset_dll, 0, cmds["MODE_REGISTER"], 200),
-				("Precharge All", 0x0400, 0, cmds["PRECHARGE_ALL"], 0),
-				("Auto Refresh", 0x0, 0, cmds["AUTO_REFRESH"], 4),
-				("Auto Refresh", 0x0, 0, cmds["AUTO_REFRESH"], 4),
-				("Load Mode Register / CL={0:d}, BL={1:d}".format(cl, bl), mr, 0, cmds["MODE_REGISTER"], 200)
-			]
-
-		elif sdram_phy.phy_settings.type == "DDR2":
-			bl = 2*sdram_phy.phy_settings.nphases
-			mr  = log2_int(bl) + (cl << 4)
-			emr = 0
-			reset_dll = 1 << 8
-
-			init_sequence = [
-				("Bring CKE high", 0x0000, 0, cmds["CKE"], 2000),
-				("Precharge All",  0x0400, 0, cmds["PRECHARGE_ALL"], 0),
-				("Load Extended Mode Register", emr, 1, cmds["MODE_REGISTER"], 0),
-				("Load Mode Register / Reset DLL, CL={0:d}, BL={1:d}".format(cl, bl), mr + reset_dll, 0, cmds["MODE_REGISTER"], 200),
-				("Precharge All", 0x0400, 0, cmds["PRECHARGE_ALL"], 0),
-				("Auto Refresh", 0x0, 0, cmds["AUTO_REFRESH"], 4),
-				("Auto Refresh", 0x0, 0, cmds["AUTO_REFRESH"], 4),
-				("Load Mode Register / CL={0:d}, BL={1:d}".format(cl, bl), mr, 0, cmds["MODE_REGISTER"], 200)
-			]
-
-		for comment, a, ba, cmd, delay in init_sequence:
-			r += gen_cmd(comment, a, ba, cmd, delay)
+	r +="\n"
+	
+	#
+	# init sequence
+	# 
+	cmds = {
+		"PRECHARGE_ALL" : "DFII_COMMAND_RAS|DFII_COMMAND_WE|DFII_COMMAND_CS",
+		"MODE_REGISTER" : "DFII_COMMAND_RAS|DFII_COMMAND_CAS|DFII_COMMAND_WE|DFII_COMMAND_CS",
+		"AUTO_REFRESH"  : "DFII_COMMAND_RAS|DFII_COMMAND_CAS|DFII_COMMAND_CS",
+		"CKE"           : "DFII_CONTROL_CKE"
+	}
+
+	def gen_cmd(comment, a, ba, cmd, delay):	
+		r = "\t/* {0} */\n".format(comment)
+		r += "\tdfii_pi0_address_write({0:#x});\n".format(a)
+		r += "\tdfii_pi0_baddress_write({0:d});\n".format(ba)
+		if "CKE" in cmd:
+			r += "\tdfii_control_write({0});\n".format(cmd)
+		else:
+			r += "\tcommand_p0({0});\n".format(cmd)
+		r += "\tcdelay({0:d});\n".format(delay)
+		r += "\n"
+		return r
 
-		r += "}\n"
-		r += "#endif\n"
 
-		return r
+	r += "static void init_sequence(void)\n{\n"
+
+	cl = sdram_phy.phy_settings.cl
+	
+	if sdram_phy.phy_settings.type == "SDR":
+		bl = 1*sdram_phy.phy_settings.nphases
+		mr  = log2_int(bl) + (cl << 4)
+		reset_dll = 1 << 8
+
+		init_sequence = [
+			("Bring CKE high", 0x0000, 0, cmds["CKE"], 2000),
+			("Precharge All",  0x0400, 0, cmds["PRECHARGE_ALL"], 0),
+			("Load Mode Register / Reset DLL, CL={0:d}, BL={1:d}".format(cl, bl), mr + reset_dll, 0, cmds["MODE_REGISTER"], 200),
+			("Precharge All", 0x0400, 0, cmds["PRECHARGE_ALL"], 0),
+			("Auto Refresh", 0x0, 0, cmds["AUTO_REFRESH"], 4),
+			("Auto Refresh", 0x0, 0, cmds["AUTO_REFRESH"], 4),
+			("Load Mode Register / CL={0:d}, BL={1:d}".format(cl, bl), mr, 0, cmds["MODE_REGISTER"], 200)
+		]
+
+	elif sdram_phy.phy_settings.type == "DDR":
+		bl = 2*sdram_phy.phy_settings.nphases
+		mr  = log2_int(bl) + (cl << 4)
+		emr = 0
+		reset_dll = 1 << 8
+
+		init_sequence = [
+			("Bring CKE high", 0x0000, 0, cmds["CKE"], 2000),
+			("Precharge All",  0x0400, 0, cmds["PRECHARGE_ALL"], 0),
+			("Load Extended Mode Register", emr, 1, cmds["MODE_REGISTER"], 0),
+			("Load Mode Register / Reset DLL, CL={0:d}, BL={1:d}".format(cl, bl), mr + reset_dll, 0, cmds["MODE_REGISTER"], 200),
+			("Precharge All", 0x0400, 0, cmds["PRECHARGE_ALL"], 0),
+			("Auto Refresh", 0x0, 0, cmds["AUTO_REFRESH"], 4),
+			("Auto Refresh", 0x0, 0, cmds["AUTO_REFRESH"], 4),
+			("Load Mode Register / CL={0:d}, BL={1:d}".format(cl, bl), mr, 0, cmds["MODE_REGISTER"], 200)
+		]
+
+	elif sdram_phy.phy_settings.type == "LPDDR":
+		bl = 2*sdram_phy.phy_settings.nphases
+		mr  = log2_int(bl) + (cl << 4)
+		emr = 0
+		reset_dll = 1 << 8
+
+		init_sequence = [
+			("Bring CKE high", 0x0000, 0, cmds["CKE"], 2000),
+			("Precharge All",  0x0400, 0, cmds["PRECHARGE_ALL"], 0),
+			("Load Extended Mode Register", emr, 2, cmds["MODE_REGISTER"], 0),
+			("Load Mode Register / Reset DLL, CL={0:d}, BL={1:d}".format(cl, bl), mr + reset_dll, 0, cmds["MODE_REGISTER"], 200),
+			("Precharge All", 0x0400, 0, cmds["PRECHARGE_ALL"], 0),
+			("Auto Refresh", 0x0, 0, cmds["AUTO_REFRESH"], 4),
+			("Auto Refresh", 0x0, 0, cmds["AUTO_REFRESH"], 4),
+			("Load Mode Register / CL={0:d}, BL={1:d}".format(cl, bl), mr, 0, cmds["MODE_REGISTER"], 200)
+		]
+
+	elif sdram_phy.phy_settings.type == "DDR2":
+		bl = 2*sdram_phy.phy_settings.nphases
+		mr  = log2_int(bl) + (cl << 4)
+		emr = 0
+		reset_dll = 1 << 8
+
+		init_sequence = [
+			("Bring CKE high", 0x0000, 0, cmds["CKE"], 2000),
+			("Precharge All",  0x0400, 0, cmds["PRECHARGE_ALL"], 0),
+			("Load Extended Mode Register", emr, 1, cmds["MODE_REGISTER"], 0),
+			("Load Mode Register / Reset DLL, CL={0:d}, BL={1:d}".format(cl, bl), mr + reset_dll, 0, cmds["MODE_REGISTER"], 200),
+			("Precharge All", 0x0400, 0, cmds["PRECHARGE_ALL"], 0),
+			("Auto Refresh", 0x0, 0, cmds["AUTO_REFRESH"], 4),
+			("Auto Refresh", 0x0, 0, cmds["AUTO_REFRESH"], 4),
+			("Load Mode Register / CL={0:d}, BL={1:d}".format(cl, bl), mr, 0, cmds["MODE_REGISTER"], 200)
+		]
+
+	for comment, a, ba, cmd, delay in init_sequence:
+		r += gen_cmd(comment, a, ba, cmd, delay)
+
+	r += "}\n"
+	r += "#endif\n"
+
+	return r