From: Clifford Wolf <clifford@clifford.at>
Date: Tue, 2 Sep 2014 20:49:24 +0000 (+0200)
Subject: Create a default selection stack in RTLIL::Design::Design()
X-Git-Tag: yosys-0.4~171
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=da360771a193707b59eac9b95b3bfe1652a057aa;p=yosys.git

Create a default selection stack in RTLIL::Design::Design()
---

diff --git a/kernel/rtlil.cc b/kernel/rtlil.cc
index f237f57ef..35cd54b46 100644
--- a/kernel/rtlil.cc
+++ b/kernel/rtlil.cc
@@ -228,6 +228,7 @@ void RTLIL::Selection::optimize(RTLIL::Design *design)
 RTLIL::Design::Design()
 {
 	refcount_modules_ = 0;
+	selection_stack.push_back(RTLIL::Selection());
 }
 
 RTLIL::Design::~Design()
diff --git a/kernel/yosys.cc b/kernel/yosys.cc
index 7b8173b6a..0ecb4cdaf 100644
--- a/kernel/yosys.cc
+++ b/kernel/yosys.cc
@@ -74,9 +74,7 @@ int SIZE(RTLIL::Wire *wire)
 void yosys_setup()
 {
 	Pass::init_register();
-
 	yosys_design = new RTLIL::Design;
-	yosys_design->selection_stack.push_back(RTLIL::Selection());
 	log_push();
 }