From: Sebastien Bourdeauducq Date: Sat, 26 Sep 2015 08:44:06 +0000 (+0800) Subject: add stream, fix CPUs and more imports. simple target boots on ppro. X-Git-Tag: 24jan2021_ls180~2106^2~43 X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=da425d1bcb62bd2b5abcbb7ef32df9b9621d2280;p=litex.git add stream, fix CPUs and more imports. simple target boots on ppro. --- diff --git a/make.py b/make.py index 28b37223..e0aa8d0d 100755 --- a/make.py +++ b/make.py @@ -7,12 +7,12 @@ import subprocess import struct import shutil -from mibuild.tools import write_to_file +from migen.build.tools import write_to_file from migen.util.misc import autotype from migen.fhdl import simplify -from misoc.soc import cpuif -from misoc.mem.sdram.phy import initsequence +from misoc.integration import cpu_interface +from misoc.integration import sdram_init from misoc_import import misoc_import @@ -81,7 +81,7 @@ if __name__ == "__main__": raise ValueError("Target has no default platform, specify a platform with -p your_platform") else: platform_name = args.platform - platform_module = misoc_import("mibuild.platforms", external_platform, platform_name) + platform_module = misoc_import("migen.build.platforms", external_platform, platform_name) platform_kwargs = dict((k, autotype(v)) for k, v in args.platform_option) platform = platform_module.Platform(**platform_kwargs) if args.external: @@ -155,25 +155,25 @@ CPU type: {} """.format(platform_name, args.target, top_class.__name__, soc.cpu_type) genhdir = os.path.join("software", "include", "generated") if soc.cpu_type != "none": - cpu_mak = cpuif.get_cpu_mak(soc.cpu_type) + cpu_mak = cpu_interface.get_cpu_mak(soc.cpu_type) write_to_file(os.path.join(genhdir, "cpu.mak"), cpu_mak) - linker_output_format = cpuif.get_linker_output_format(soc.cpu_type) + linker_output_format = cpu_interface.get_linker_output_format(soc.cpu_type) write_to_file(os.path.join(genhdir, "output_format.ld"), linker_output_format) - linker_regions = cpuif.get_linker_regions(memory_regions) + linker_regions = cpu_interface.get_linker_regions(memory_regions) write_to_file(os.path.join(genhdir, "regions.ld"), boilerplate + linker_regions) for sdram_phy in ["sdrphy", "ddrphy"]: if hasattr(soc, sdram_phy): - sdram_phy_header = initsequence.get_sdram_phy_header(getattr(soc, sdram_phy).settings) + sdram_phy_header = sdram_init.get_sdram_phy_header(getattr(soc, sdram_phy).settings) write_to_file(os.path.join(genhdir, "sdram_phy.h"), boilerplate + sdram_phy_header) - mem_header = cpuif.get_mem_header(memory_regions, getattr(soc, "flash_boot_address", None)) + mem_header = cpu_interface.get_mem_header(memory_regions, getattr(soc, "flash_boot_address", None)) write_to_file(os.path.join(genhdir, "mem.h"), boilerplate + mem_header) - csr_header = cpuif.get_csr_header(csr_regions, soc.get_constants()) + csr_header = cpu_interface.get_csr_header(csr_regions, soc.get_constants()) write_to_file(os.path.join(genhdir, "csr.h"), boilerplate + csr_header) if actions["build-csr-csv"]: - csr_csv = cpuif.get_csr_csv(csr_regions) + csr_csv = cpu_interface.get_csr_csv(csr_regions) write_to_file(args.csr_csv, csr_csv) if actions["build-bios"]: diff --git a/misoc/cores/lm32/__init__.py b/misoc/cores/lm32/__init__.py new file mode 100644 index 00000000..c2727f48 --- /dev/null +++ b/misoc/cores/lm32/__init__.py @@ -0,0 +1 @@ +from misoc.cores.lm32.core import LM32 diff --git a/misoc/cores/lm32/core.py b/misoc/cores/lm32/core.py index ca9b001c..fd1b1e95 100644 --- a/misoc/cores/lm32/core.py +++ b/misoc/cores/lm32/core.py @@ -1,7 +1,8 @@ import os from migen import * -from migen.bus import wishbone + +from misoc.interconnect import wishbone class LM32(Module): @@ -54,10 +55,12 @@ class LM32(Module): ] # add Verilog sources - platform.add_sources(os.path.join("extcores", "lm32", "submodule", "rtl"), + vdir = os.path.join( + os.path.abspath(os.path.dirname(__file__)), "verilog") + platform.add_sources(os.path.join(vdir, "submodule", "rtl"), "lm32_cpu.v", "lm32_instruction_unit.v", "lm32_decoder.v", "lm32_load_store_unit.v", "lm32_adder.v", "lm32_addsub.v", "lm32_logic_op.v", "lm32_shifter.v", "lm32_multiplier.v", "lm32_mc_arithmetic.v", "lm32_interrupt.v", "lm32_ram.v", "lm32_dp_ram.v", "lm32_icache.v", "lm32_dcache.v", "lm32_debug.v", "lm32_itlb.v", "lm32_dtlb.v") - platform.add_verilog_include_path(os.path.join("extcores", "lm32")) + platform.add_verilog_include_path(vdir) diff --git a/misoc/cores/lm32/verilog/submodule b/misoc/cores/lm32/verilog/submodule new file mode 160000 index 00000000..84b3e3ca --- /dev/null +++ b/misoc/cores/lm32/verilog/submodule @@ -0,0 +1 @@ +Subproject commit 84b3e3ca0ad9535acaef201c1482342871358b08 diff --git a/misoc/cores/mor1kx/__init__.py b/misoc/cores/mor1kx/__init__.py index e69de29b..e92714ae 100644 --- a/misoc/cores/mor1kx/__init__.py +++ b/misoc/cores/mor1kx/__init__.py @@ -0,0 +1 @@ +from misoc.cores.mor1kx.core import MOR1KX diff --git a/misoc/cores/mor1kx/core.py b/misoc/cores/mor1kx/core.py index f9c69642..a4b5e0d0 100644 --- a/misoc/cores/mor1kx/core.py +++ b/misoc/cores/mor1kx/core.py @@ -1,7 +1,8 @@ import os from migen import * -from migen.bus import wishbone + +from misoc.interconnect import wishbone class MOR1KX(Module): @@ -76,5 +77,7 @@ class MOR1KX(Module): ] # add Verilog sources - platform.add_source_dir(os.path.join("extcores", "mor1kx", "submodule", - "rtl", "verilog")) + vdir = os.path.join( + os.path.abspath(os.path.dirname(__file__)), + "verilog", "rtl", "verilog") + platform.add_source_dir(vdir) diff --git a/misoc/cores/mor1kx/verilog b/misoc/cores/mor1kx/verilog new file mode 160000 index 00000000..fb519d01 --- /dev/null +++ b/misoc/cores/mor1kx/verilog @@ -0,0 +1 @@ +Subproject commit fb519d011ae2524e3681f07b206df0a6c03f82a8 diff --git a/misoc/cores/uart/core.py b/misoc/cores/uart/core.py index 9b6f7f5c..b6a2a703 100644 --- a/misoc/cores/uart/core.py +++ b/misoc/cores/uart/core.py @@ -1,10 +1,10 @@ from migen import * from migen.genlib.record import Record +from migen.genlib.cdc import MultiReg from misoc.interconnect.csr import * from misoc.interconnect.csr_eventmanager import * -# TODO: from migen.actorlib.fifo import SyncFIFO, AsyncFIFO -# TODO: remove dataflow? +from misoc.interconnect.stream import Source, Sink, SyncFIFO, AsyncFIFO class RS232PHYRX(Module): diff --git a/misoc/integration/soc_core.py b/misoc/integration/soc_core.py index bb2eb6c3..93d08525 100644 --- a/misoc/integration/soc_core.py +++ b/misoc/integration/soc_core.py @@ -94,7 +94,8 @@ class SoCCore(Module): self.register_mem("main_ram", self.mem_map["main_ram"], self.main_ram.bus, integrated_main_ram_size) if with_csr: - self.submodules.wishbone2csr = wishbone2csr.WB2CSR(bus_csr=csr.Interface(csr_data_width, csr_address_width)) + self.submodules.wishbone2csr = wishbone2csr.WB2CSR( + bus_csr=csr_bus.Interface(csr_data_width, csr_address_width)) self.register_mem("csr", self.mem_map["csr"], self.wishbone2csr.wishbone) if with_uart: diff --git a/misoc/interconnect/csr_bus.py b/misoc/interconnect/csr_bus.py index 1a755528..85a7c030 100644 --- a/misoc/interconnect/csr_bus.py +++ b/misoc/interconnect/csr_bus.py @@ -1,6 +1,7 @@ from migen import * from migen.genlib.record import * from migen.genlib.misc import chooser +from migen.util.misc import xdir from misoc.interconnect import csr from misoc.interconnect.csr import CSRStorage @@ -108,7 +109,7 @@ class CSRBank(csr.GenericBank): ### - GenericBank.__init__(self, description, flen(self.bus.dat_w)) + csr.GenericBank.__init__(self, description, flen(self.bus.dat_w)) sel = Signal() self.comb += sel.eq(self.bus.adr[9:] == address) @@ -154,7 +155,7 @@ class CSRBankArray(Module): mapaddr = self.address_map(name, memory) if mapaddr is None: continue - sram_bus = csr.Interface(*ifargs, **ifkwargs) + sram_bus = Interface(*ifargs, **ifkwargs) mmap = csr.SRAM(memory, mapaddr, bus=sram_bus) self.submodules += mmap csrs += mmap.get_csrs() @@ -163,8 +164,8 @@ class CSRBankArray(Module): mapaddr = self.address_map(name, None) if mapaddr is None: continue - bank_bus = csr.Interface(*ifargs, **ifkwargs) - rmap = Bank(csrs, mapaddr, bus=bank_bus) + bank_bus = Interface(*ifargs, **ifkwargs) + rmap = CSRBank(csrs, mapaddr, bus=bank_bus) self.submodules += rmap self.banks.append((name, csrs, mapaddr, rmap)) diff --git a/misoc/interconnect/stream.py b/misoc/interconnect/stream.py new file mode 100644 index 00000000..cc40b957 --- /dev/null +++ b/misoc/interconnect/stream.py @@ -0,0 +1,122 @@ +from migen import * +from migen.genlib.record import * +from migen.genlib import fifo + + +def _make_m2s(layout): + r = [] + for f in layout: + if isinstance(f[1], (int, tuple)): + r.append((f[0], f[1], DIR_M_TO_S)) + else: + r.append((f[0], _make_m2s(f[1]))) + return r + + +class EndpointDescription: + def __init__(self, payload_layout, param_layout=[], packetized=False): + self.payload_layout = payload_layout + self.param_layout = param_layout + self.packetized = packetized + + def get_full_layout(self): + reserved = {"stb", "ack", "payload", "param", "sop", "eop", "description"} + attributed = set() + for f in self.payload_layout + self.param_layout: + if f[0] in attributed: + raise ValueError(f[0] + " already attributed in payload or param layout") + if f[0] in reserved: + raise ValueError(f[0] + " cannot be used in endpoint layout") + attributed.add(f[0]) + + full_layout = [ + ("payload", _make_m2s(self.payload_layout)), + ("param", _make_m2s(self.param_layout)), + ("stb", 1, DIR_M_TO_S), + ("ack", 1, DIR_S_TO_M) + ] + if self.packetized: + full_layout += [ + ("sop", 1, DIR_M_TO_S), + ("eop", 1, DIR_M_TO_S) + ] + return full_layout + + +class _Endpoint(Record): + def __init__(self, description_or_layout): + if isinstance(description_or_layout, EndpointDescription): + self.description = description_or_layout + else: + self.description = EndpointDescription(description_or_layout) + Record.__init__(self, self.description.get_full_layout()) + + def __getattr__(self, name): + try: + return getattr(object.__getattribute__(self, "payload"), name) + except: + return getattr(object.__getattribute__(self, "param"), name) + + +class Source(_Endpoint): + def connect(self, sink): + return Record.connect(self, sink) + + +class Sink(_Endpoint): + def connect(self, source): + return source.connect(self) + + +class _FIFOWrapper(Module): + def __init__(self, fifo_class, layout, depth): + self.sink = Sink(layout) + self.source = Source(layout) + self.busy = Signal() + + ### + + description = self.sink.description + fifo_layout = [ + ("payload", description.payload_layout), + # Note : Can be optimized by passing parameters + # in another fifo. We will only have one + # data per packet. + ("param", description.param_layout) + ] + if description.packetized: + fifo_layout += [("sop", 1), ("eop", 1)] + + self.submodules.fifo = fifo_class(fifo_layout, depth) + + self.comb += [ + self.sink.ack.eq(self.fifo.writable), + self.fifo.we.eq(self.sink.stb), + self.fifo.din.payload.eq(self.sink.payload), + self.fifo.din.param.eq(self.sink.param), + + self.source.stb.eq(self.fifo.readable), + self.source.payload.eq(self.fifo.dout.payload), + self.source.param.eq(self.fifo.dout.param), + self.fifo.re.eq(self.source.ack) + ] + if description.packetized: + self.comb += [ + self.fifo.din.sop.eq(self.sink.sop), + self.fifo.din.eop.eq(self.sink.eop), + self.source.sop.eq(self.fifo.dout.sop), + self.source.eop.eq(self.fifo.dout.eop) + ] + + +class SyncFIFO(_FIFOWrapper): + def __init__(self, layout, depth, buffered=False): + _FIFOWrapper.__init__( + self, + fifo.SyncFIFOBuffered if buffered else fifo.SyncFIFO, + layout, depth) + + +class AsyncFIFO(_FIFOWrapper): + def __init__(self, layout, depth): + _FIFOWrapper.__init__(self, fifo.AsyncFIFO, layout, depth) diff --git a/software/common.mak b/software/common.mak index cff9bbd3..053ace1c 100644 --- a/software/common.mak +++ b/software/common.mak @@ -21,7 +21,7 @@ AR_quiet = @echo " AR " $@ && $(AR_normal) LD_quiet = @echo " LD " $@ && $(LD_normal) OBJCOPY_quiet = @echo " OBJCOPY " $@ && $(OBJCOPY_normal) -MSC_GIT_ID := $(shell cd $(MSCDIR) && $(PYTHON) -c "from misoc.cpu.identifier import get_id; print(hex(get_id()), end='')") +MSC_GIT_ID := $(shell cd $(MSCDIR) && $(PYTHON) -c "from misoc.cores.identifier import get_id; print(hex(get_id()), end='')") ifeq ($(V),1) CC = $(CC_normal)